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general description the max9288/max9290 gigabit multimedia serial link (gmsl) deserializers receive data from a gmsl serializer over 50 coax or 100 shielded twisted-pair (stp) cable and output deserialized data on the csi-2 outputs. the max9290 has hdcp content protection but other- wise is the same as the max9288. the deserializers pair with any gmsl serializer capable of coax output. when programmed for stp input, they are backward compatible with any gmsl serializer. the audio channel supports l-pcm i 2 s stereo and up to eight channels of l-pcm in tdm mode. sample rates of 32khz to 192khz are supported with sample depth up to 32 bits. the embedded control channel operates at 9.6kbps to 1mbps in uart-to-uart and uart-to-i 2 c modes, and up to 1mbps in i 2 c-to-i 2 c mode. using the control channel, a c can program serializer, deserializer, and peripheral device registers at any time, independent of video timing, and manage hdcp operation (max9290). two gpio ports are included, allowing display power- up and switching of the backlight, among other uses. a continuously sampled gpi input supports touch-screen controller interrupt requests in display applications. for use with longer cables, the deserializers have a pro- grammable cable equalizer. the serial input meets iso 10605 and iec 61000-4-2 esd standards. the gmsl supply is 3.0v to 3.6v, the mipi csi-2 supply is 1.7v to 1.9v, and the i/o supply is 1.7v to 3.6v. the devices are available in lead(pb)-free, 48-pin, 7mm x 7mm tqfn and qfnd packages with exposed pad and 0.5mm lead pitch. applications high-resolution automotive navigation rear-seat infotainment megapixel camera systems beneits and features ideal for high-definition video applications ? 4-lane csi-2 output with up to 1gbps per lane ? works with low-cost 50 coax cable and fakra connectors or 100 stp ? 104mhz high-bandwidth mode supports 1920 x 720p/60hz display with 24-bit color ? equalization allows 15m cable at full speed ? up to 192khz sample rate and 32-bit sample depth for 7.1 channel hd audio ? audio clock from audio source or audio sink ? color lookup table for gamma correction ? cntl0Ccntl3 control outputs for hdmi/mhl multiple data rates for system flexibility ? up to 3.12gbps serial-bit rate ? 6.25mhz to 104mhz pixel clock ? 9.6kbps to 1mbps control channel in uart, mixed uart/i 2 c, or i 2 c mode with clock-stretch capability reduces emi and shielding requirements ? tracks spread spectrum on input ? high-immunity mode for maximum control- channel noise rejection peripheral features for system power-up and verification ? built-in prbs tester for ber testing of the serial link ? programmable choice of 8 default device addresses ? two dedicated gpio ports ? dedicated up/down gpi for touch-screen interrupt and other uses ? remote/local wake-up from sleep mode meets rigorous automotive and industrial requirements ? -40c to +105c operating temperature ? 8kv contact and 12kv air iso 10605 and iec 61000-4-2 esd protection ordering information appears at end of data sheet. 19-6916; rev 2; 11/14 max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output simpliied diagram c gmsl serializer max9288 max9290 video/audio i 2 c 720p display csi-2 video/ audio i 2 c downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 2 table of contents general description ............................................................................ 1 applications .................................................................................. 1 benefits and features .......................................................................... 1 absolute maximum ratings ...................................................................... 8 package thermal characteristics (note 2) .......................................................... 8 dc electrical characteristics ..................................................................... 8 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 typical operating characteristics ................................................................ 16 pin configuration ............................................................................. 18 pin description ............................................................................... 18 functional diagram ........................................................................... 21 detailed description ........................................................................... 27 register mapping .................................................. ......................... 27 output bit map .................................................. ........................... 28 serial link signaling and data format ................................................... ........ 28 gmsl-to-csi-2 conversion and output ................................................... ....... 28 video data operation .................................................. ................... 28 auto pixel-per-line feature ................................................... .............. 48 clock operation ................................................... ....................... 49 data-rate selection and csi-2 clock limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 gmsl clock range. .................................................. .................... 50 csi-2 clock range .................................................. ..................... 50 high-bandwidth mode .................................................. ..................... 50 audio channel ................................................... ........................... 50 audio channel input .................................................. .................... 50 audio channel output .................................................. ................... 58 additional mclk output for audio applications ................................................. 58 audio output timing sources .................................................. ............. 58 reverse control channel .................................................. ................... 58 control channel and register programming ................................................... . 59 uart interface .................................................. ........................ 59 interfacing command-byte-only i 2 c devices with uart ......................................... 61 uart bypass mode .................................................. .................... 61 i 2 c interface .................................................. ............................. 62 start and stop conditions .................................................. ............. 63 bit transfer ................................................... ........................... 63 downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 3 table of contents ( continued) acknowledge .................................................. .......................... 63 slave address .................................................. ......................... 64 bus reset ................................................... ............................ 65 format for reading .................................................. ..................... 66 i 2 c communication with remote-side devices ................................................. 66 i 2 c address translation .................................................. .................... 67 gpo/gpi control .................................................. ......................... 67 line equalizer .................................................. ............................ 67 hs/vs/de tracking ................................................... ....................... 67 serial input .................................................. .............................. 67 coax splitter mode ................................................... ....................... 68 cable type configuration input .................................................. .............. 69 color lookup tables ................................................... ...................... 69 programming and verifying lut data ................................................... ...... 69 lut color translation .................................................. ................... 69 lut bit width ................................................... ......................... 70 recommended lut program procedure .................................................. .... 70 high-immunity reverse control-channel mode ................................................... . 71 sleep mode ................................................... ............................. 71 power-down mode .................................................. ........................ 71 configuration link ................................................... ........................ 72 link startup procedure ................................................... .................... 72 high-bandwidth digital content protection (hdcp) .................................................. 73 encryption enable ................................................... ........................ 73 synchronization of encryption .................................................. ............... 73 repeater support .................................................. ......................... 73 hdcp authentication procedures ................................................................. 74 hdcp protocol summary ................................................... .................. 74 example repeater networktwo cs ................................................... ..... 78 detection and action upon new device connection ................................................ 78 notification of start of authentication and enable of enc ryption to downstream links ..................... 82 applications information ........................................................................ 82 self prbs test ................................................... .......................... 82 error checking .................................................. ........................... 82 err output .................................................. ............................. 82 downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 4 table of contents ( continued) auto error reset ................................................... ......................... 83 dual c control .................................................. .......................... 83 changing the clock frequency ................................................... .............. 83 spread-spectrum clock tracking ................................................... ............ 83 fast detection of loss-of-synchronization ................................................... ..... 83 providing a frame sync (camera applications) ................................................... . 83 software programming of the device addresses ................................................... 83 three-level configuration inputs ................................................... ............ 84 configuration blocking .................................................. ..................... 84 compatibility with other gmsl devices .................................................. ....... 84 key memory .................................................. ............................. 84 hs/vs/de inversion .................................................. ....................... 84 ws/sck inversion .................................................. ........................ 84 gpios .................................................. .................................. 84 line-fault detection .................................................. ....................... 84 internal input pulldowns .................................................. .................... 85 choosing i 2 c/uart pullup resistors .................................................. ......... 85 ac-coupling .................................................. ............................. 85 selection of ac-coupling capacitors ................................................... ......... 85 power-supply circuits and bypassing .................................................. ......... 85 power-supply table .................................................. ....................... 85 cables and connectors .................................................. .................... 85 board layout ................................................... ............................ 85 esd protection .................................................. ........................... 87 typical application circuit ..................................................................... 102 ordering information ......................................................................... 102 chip information ............................................................................. 102 package information ......................................................................... 102 revision history ............................................................................. 103 downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 5 list of figures figure 1. line fault ........................................................................... 22 figure 2. reverse control-channel output parameters ............................................... 23 figure 3. test circuit for differential input measurement .............................................. 23 figure 4. test circuit for single-ended input measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 5. worst-case pattern output ............................................................. 24 figure 6. i 2 c timing parameters ................................................................. 24 figure 7. output rise-and-fall times ............................................................. 25 figure 8. deserializer delay ..................................................................... 25 figure 9. gpi-to-gpo delay .................................................................... 26 figure 10. lock time .......................................................................... 26 figure 11. power-up delay ..................................................................... 26 figure 12. output i 2 s timing parameters .......................................................... 26 figure 13. mipi output timing parameters ......................................................... 27 figure 14. 24-bit mode serial data format ......................................................... 29 figure 15. 32-bit mode serial data format ......................................................... 29 figure 16. high-bandwidth mode serial-data format ................................................ 30 figure 17. transmitting a frame from gmsl to mipi ................................................. 30 figure 18. rgb565 output ..................................................................... 31 figure 19. rgb666 output ..................................................................... 32 figure 20. rgb888 output ..................................................................... 33 figure 21. yuv422 8-bit (muxed) output .......................................................... 34 figure 22. yuv422 10-bit (muxed) output ......................................................... 35 figure 23. yuv422 8-bit output ................................................................. 36 figure 24. yuv422 10-bit output ................................................................ 37 figure 25. yuv422 12-bit output ................................................................ 38 figure 26. raw 8-bit (double load) output ........................................................ 39 figure 27. raw 10-bit (double load) output ....................................................... 40 figure 28. raw 12-bit (double load) output ........................................................ 41 figure 29. raw 8-bit output .................................................................... 42 figure 30. raw 10-bit output ................................................................... 43 figure 31. raw 12-bit output ................................................................... 44 downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 6 list of figures ( continued) figure 32. raw 14-bit output ................................................................... 45 figure 33. user-defined 24-bit output ............................................................ 46 figure 34. user-defined 24-bit output ............................................................ 47 figure 35. audio channel input format ............................................................ 50 figure 36. 8-channel tdm (24-bit samples, padded with zeros ) ....................................... 57 figure 37. 6-channel tdm (24-bit samples, no padding) ............................................. 57 figure 38. stereo i 2 s (24-bit samples, padded with zeros) ........................................... 57 figure 39. stereo i 2 s (16-bit samples, no padding) ................................................. 58 figure 40. audio channel output format .......................................................... 59 figure 41. gmsl uart protocol for base mode .................................................... 60 figure 42. gmsl uart data format for base mode ................................................. 60 figure 43. sync byte (0x79) .................................................................... 60 figure 44. ack byte (0xc3) ..................................................................... 60 figure 45. format conversion between gmsl uart and i 2 c with register address (i2cmethod = 0) ........ 61 figure 46. format conversion between gmsl uart and i 2 c with register address (i2cmethod = 1) ........ 62 figure 47. start and stop conditions ........................................................... 63 figure 48. bit transfer ......................................................................... 63 figure 49. acknowledge ........................................................................ 64 figure 50. slave address ....................................................................... 64 figure 51. format for i 2 c write .................................................................. 65 figure 52. format for write to multiple registers .................................................... 65 figure 53. format for i 2 c read .................................................................. 66 figure 54. 2:1 coax splitter connection diagram .................................................... 68 figure 55. coax connection diagram ............................................................. 68 figure 56. lut dataflow ....................................................................... 70 figure 57. state diagram (cds = high) ............................................................ 78 figure 58. example network with one repeater and tw o cs (tx = gmsl serializers, rx = deserializers) ..... 78 figure 59. human body model esd test circuit ..................................................... 87 figure 60. iec 61000-4-2 contact discharge esd test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 61. iso 10605 contact discharge esd test circuit ............................................ 87 downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 7 list of tables table 1. device address defaults (register 0x00, 0x01) .............................................. 28 table 2 video output map (rgb and yuv) ........................................................ 48 table 3. video output map (raw and user defined) ................................................ 49 table 4. control output map .................................................................... 51 table 5. gmsl data-rate selection table ......................................................... 51 table 6 input pixel clock range (mhz) ............................................................ 51 table 7. output csi-2 data rate range (mbps) ..................................................... 54 table 8. maximum audio ws frequency (khz) for various pixel clo ck frequencies ......................... 56 table 9. f src settings ........................................................................ 59 table 10. i 2 c bit-rate ranges .................................................................. 66 table 11. cable equalizer boost levels ............................................................ 67 table 12. configuration input map ................................................................ 69 table 13 pixel data format ..................................................................... 69 table 14. reverse control-channel modes ......................................................... 71 table 15. fast high-immunity mode requirements ................................................... 71 table 16. startup procedure for image-sensing appli cations (cds = high, figure 58) ...................... 72 table 17. startup, hdcp authentication, and normal operatio n (deserializer is not a repeater)first part of the hdcp authentication protocol .................................................................... 74 table 18. link integrity check (normal)performed every 128 f rames after encryption is enabled ........... 76 table 19. optional enhanced link integrity checkperforme d every 16 frames after encryption is enabled .... 77 table 20. hdcp authentication and normal operation (one repe ater, two cs)first and second parts of the hdcp authentication protocol ................................................................... 79 table 21. max9288/max9290 feature compatibility ................................................. 84 table 22. line-fault mapping ................................................................... 86 table 23. additional supply current from hdcp (max9290 only) ....................................... 86 table 24. suggested connectors and cables for gmsl ............................................... 86 table 25. register table ....................................................................... 88 table 26. hdcp register table (max9290 only) ................................................... 100 downloaded from: http:///
(note 1) avdd3 to ep ........................................................-0.5v to +3.9v avdd18, dvdd18 to ep ......................................-0.5v to +1.9v iovdd to ep ........................................................-0.5v to +3.9v in+, in- to ep .......................................................-0.5v to +1.9v lmn_ to ep (15ma current limit)..........................-0.5v to +3.9v clk_, dout_ to ep ............................................-0.5v to +1.9v all other pins to ep ............................-0.5v to (v iovdd + 0.5v) in+, in- short circuit to ground or supply ...............continuous continuous power dissipation (t a = +70c) tqfn (derate 40mw/c above +70c) .....................3200mw qfnd (derate 38.5mwc above +70c) ...............3076.9mw junction temperature ......................................................+150c storage temperature ........................................ -65c to +150c lead temperature (soldering, 10s) ................................. +300c soldering temperature (reflow) .......................................+260c tqfn junction-to-ambient thermal resistance ( ja ) ..........25c/w junction-to-case thermal resistance ( jc ) ..................... 1c qfnd junction-to-ambient thermal resistance ( ja ) ..........26c/w junction-to-case thermal resistance ( jc ) ..................... 1c (v avdd18 = v dvdd18 = 1.7v to 1.9v, v avdd3 = 3.0v to 3.6v, v iovdd = 1.7v to 3.6v, r l = 100 1% (differential), ep connected to pcb ground (gnd), t a = -40c to +105c, unless otherwise noted. typical values are at v avdd18 = v dvdd18 = v iovdd = 1.8v, v avdd3 = 3.3v, t a = +25c.) (note 3) note 1: ep connected to pcb ground. max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 8 parameter symbol conditions min typ max units single-ended inputs (add_, i2csel, pwdn , ms, gpi, drs, eqs, cds, him, sck, ws) high-level input voltage v ih1 0.65 x v iovdd v low-level input voltage v il1 0.35 x v iovdd v input current i in1 v in = 0v to v iovdd -20 +20 a three-level logic inputs (bws, cx/tp) high-level input voltage v ih 0.7 x v iovdd v low-level input voltage v il 0.3 x v iovdd v mid-level input current i inm (note 4) -10 +10 a input current i in -150 +150 a single-ended outputs (ws, sck, sd, cntl_, intout) high-level output voltage v oh1 i out = -2ma dcs = 0 v iovdd - 0.3 v dcs = 1 v iovdd - 0.2 low-level output voltage v ol1 i out = 2ma dcs = 0 0.3 v dcs = 1 0.2 dc electrical characteristics stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics (note 2) absolute maximum ratings note 2: package thermal resistances were obtained using the method described in jedec specification jesd51- 7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . downloaded from: http:///
(v avdd18 = v dvdd18 = 1.7v to 1.9v, v avdd3 = 3.0v to 3.6v, v iovdd = 1.7v to 3.6v, r l = 100 1% (differential), ep connected to pcb ground (gnd), t a = -40c to +105c, unless otherwise noted. typical values are at v avdd18 = v dvdd18 = v iovdd = 1.8v, v avdd3 = v iovdd = 3.3v, t a = +25c.) max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 9 parameter symbol conditions min typ max units output short-circuit current i os v o = 0v, dcs = 0 v iovdd = 3.0v to 3.6v 15 25 39 ma v iovdd = 1.7v to 1.9v 3 7 15 v o = 0v, dcs = 1 v iovdd = 3.0v to 3.6v 20 35 63 v iovdd = 1.7v to 1.9v 5 10 21 mipi high-speed differential output ports (dout0Cdout3_, clk_) (note 3) transmit static common-mode voltage v cmtx 150 200 250 mv v cmtx mismatch when output is differential 1 or 0 |v cmt(1,0) | 5 mv transmit differential voltage |v od | 140 200 270 mv v od mismatch when output is differential 1 or 0 |v od | 14 mv output high voltage v ohhs 360 mv single-ended output impedance z os 40 50 62.5 ? single-ended output impedance mismatch z os mismatch of the single-ended output impedance at both dout_+ and dout_- pins for both differential 1 and 0 10 % mipi low-speed single-ended output ports (dout0Cdout3_, clk_) thevenin output high level v oh 1.05 1.2 1.3 v thevenin output low level v ol -50 +50 mv output impedance of low power transmitter z olp 110 ? open-drain input/output (gpio0, gpio1, rx/sda, tx/scl, err , lock, lflt ) high-level input voltage v ih2 0.7 x v iovdd v low-level input voltage v il2 0.3 x v iovdd v input current i in2 (note 5) rx/sda, tx/scl -100 +5 a lock, err , gpio_, lflt -80 +5 low-level output voltage v ol2 i out = 3ma v iovdd = 1.7v to 1.9v 0.4 v v iovdd = 3.0v to 3.6v 0.3 input capacitance c in each pin (note 6) 10 pf line-fault detection input (lmn0, lmn1) short-to-gnd threshold v tg figure 1 0.3 v normal threshold v tn figure 1 0.57 1.07 v open threshold v to figure 1 1.45 v io + 0.06 v open input voltage v io figure 1 1.49 1.75 v dc electrical characteristics (continued) downloaded from: http:///
(v avdd18 = v dvdd18 = 1.7v to 1.9v, v avdd3 = 3.0v to 3.6v, v iovdd = 1.7v to 3.6v, r l = 100 1% (differential), ep connected to pcb ground (gnd), t a = -40c to +105c, unless otherwise noted. typical values are at v avdd18 = v dvdd18 = v iovdd = 1.8v, v avdd3 = 3.3v, t a = +25c.) max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 10 parameter symbol conditions min typ max units short-to-battery threshold v tb figure 1 2.47 v output for reverse control channel (in+, in-) differential high output peak voltage (v in+ ) - (v in- ) v rodh forward channel disabled, figure 2 legacy reverse control-channel mode 30 60 mv high-immunity mode 50 100 differential low output peak voltage (v in+ ) - (v in- ) v rodl forward channel disabled, figure 2 legacy reverse control-channel mode -60 -30 mv high-immunity mode -100 -50 single-ended high output peak voltage v rosh forward channel disabled legacy reverse control-channel mode 30 60 mv high-immunity mode 50 100 single-ended low output peak voltage v rosl forward channel disabled legacy reverse control-channel mode -60 -30 mv high-immunity mode -100 -50 differential inputs (in+, in-) differential high input threshold (peak) voltage (v in+ ) - (v in- ) v idh(p) figure 3 activity detector medium threshold, (0x0b d[6:5] = 01) 60 mv activity detector low threshold, (0x0b d[6:5] = 00) 52 differential low input threshold (peak) voltage (v in+ ) - (v in- ) v idl(p) figure 3 activity detector medium threshold, (0x0b d[6:5] = 01) -60 mv activity detector low threshold, (0x0b d[6:5] = 00) -52 input common-mode voltage ((v in+ ) + (v in- ))/2 v cmr 1 1.3 1.6 v differential input resistance (internal) r in 80 100 130 single-ended inputs (in+, in-)single-ended high input threshold (peak) voltage v ish(p) figure 4 activity detector medium threshold, (0x0b d[6:5] = 01) 43 mv activity detector low threshold, (0x0b d[6:5] = 00) 36 single-ended low input threshold (peak) voltage v isl(p) figure 4 activity detector medium threshold, (0x0b d[6:5] = 01) -43 mv activity detector low threshold, (0x0b d[6:5] = 00) -36 input resistance (internal) r i 40 50 65 dc electrical characteristics (continued) downloaded from: http:///
(v avdd18 = v dvdd18 = 1.7v to 1.9v, v avdd3 = 3.0v to 3.6v, v iovdd = 1.7v to 3.6v, r l = 100 1% (differential), ep connected to pcb ground (gnd), t a = -40c to +105c, unless otherwise noted. typical values are at v avdd18 = v dvdd18 = v iovdd = 1.8v, v avdd3 = 3.3v, t a = +25c.) (note 3) max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 11 parameter symbol conditions min typ max units power supply total supply current (avdd_ + dvdd_ + iovdd) (note 7) (worst-case-pattern, figure 5) i wcs bws = low, f pclkout = 16.6mhz, 1 mipi lane, rgb666 avdd3 97 131 ma dvdd18 28 38 iovdd 0.3 2 avdd18 21 33 total 146 197 bws = low, f pclkout = 33.3mhz, 1 mipi lanes, rgb666 avdd3 99 134 dvdd18 45 62 iovdd 0.3 2 avdd18 25 34 total 170 227 bws = low, f pclkout = 66.6mhz, 2 mipi lanes, rgb666 avdd3 103 140 dvdd18 69 94 iovdd 0.3 2 avdd18 29 39 total 201 270 bws = low, f pclkout = 104mhz, 2 mipi lanes, rgb666 avdd3 112 152 dvdd18 100 139 iovdd 0.3 2 avdd18 46 63 total 259 351 bws = mid, f pclkout = 36.6mhz, 1 mipi lanes, rgb888 avdd3 100 136 dvdd18 51 70 iovdd 0.3 2 avdd18 27 36 total 178 236 bws = mid, f pclkout = 104mhz, 2 mipi lanes, rgb888 avdd3 112 153 dvdd18 123 169 iovdd 0.3 2 avdd18 55 75 total 290 394 sleep-mode supply current i ccs 44 120 a power-down current i ccz pwdn = gnd 12 75 a esd protection in+, in- (note 8) v esd human body model, r d = 1.5k, c s = 100pf 8 kv iec 61000-4-2, r d = 330, c s = 150pf contact discharge 8 air discharge 12 iso 10605, r d = 2k, c s = 330pf contact discharge 8 air discharge 20 all other pins (note 9) v esd human body model, r d = 1.5k, c s = 100pf 2.5 kv dc electrical characteristics (continued) downloaded from: http:///
(v avdd18 = v dvdd18 = 1.7v to 1.9v, v avdd3 = 3.0v to 3.6v, v iovdd = 1.7v to 3.6v, r l = 100 1% (differential), ep connected to pcb ground (gnd), t a = -40c to +105c, unless otherwise noted. typical values are at v avdd18 = v dvdd18 = v iovdd = 1.8v, v avdd3 = 3.3v, t a = +25c.) max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 12 parameter symbol conditions min typ max units i 2 c/uart port timing i 2 c/uart bit rate 9.6 1000 kbps output rise time t r 30% to 70%, c l = 10pf to 100pf, 1k pullup to v iovdd 20 150 ns output fall time t f 70% to 30%, c l = 10pf to 100pf, 1k pullup to v iovdd 20 150 ns i 2 c timing (figure 6) scl clock frequency f scl low f scl range: (i2cmstbt = 010, i2cslvsh = 10) 9.6 100 khz mid f scl range: (i2cmstbt 101, i2cslvsh = 01) > 100 400 high f scl range: (i2cmstbt = 111, i2cslvsh = 00) > 400 1000 start condition hold time t hd:sta f scl range low 4.0 s mid 0.6 high 0.26 low period of scl clock t low f scl range low 4.7 s mid 1.3 high 0.5 high period of scl clock t high f scl range low 4.0 s mid 0.6 high 0.26 repeated start condition setup time t su:sta f scl range low 4.7 s mid 0.6 high 0.26 data hold time t hd:dat f scl range low 0 s mid 0 high 0 data setup time t su:dat f scl range low 250 s mid 100 high 50 setup time for stop condition t su:sto f scl range low 4.0 s mid 0.6 high 0.26 bus free time t buf f scl range low 4.7 s mid 1.3 high 0.5 ac electrical characteristics downloaded from: http:///
(v avdd18 = v dvdd18 = 1.7v to 1.9v, v avdd3 = 3.0v to 3.6v, v iovdd = 1.7v to 3.6v, r l = 100 1% (differential), ep connected to pcb ground (gnd), t a = -40c to +105c, unless otherwise noted. typical values are at v avdd18 = v dvdd18 = v iovdd = 1.8v, v avdd3 = 3.3v, t a = +25c.) max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 13 parameter symbol conditions min typ max units data valid time t vd:dat f scl range low 3.45 s mid 0.9 high 0.45 data valid acknowledge time t vd:ack f scl range low 3.45 s mid 0.9 high 0.45 pulse width of spikes suppressed t sp f scl range low 50 ns mid 50 high 50 capacitive load each bus line c b (note 8) 100 pf switching characteristics (note 10)deserializer delay t sd (note 11) figure 8 1388 1500 bits reverse control-channel output rise time t r no forward channel data transmission, figure 2 180 400 ns reverse control-channel output fall time t f no forward channel data transmission, figure 2 180 400 ns gpi-to-gpo delay t gpio deserializer gpi to serializer gpo (cable delay not included), figure 9 350 s lock time t lock figure 10 (note 12) 4 ms power-up time t pu figure 11 8.5 ms i 2 s/tdm output timing (note 10) ws jitter tj ws t ws = 1/f ws , (cycle-to-cycle), rising-to-falling edge or falling-to- rising edge f ws = 48khz or 44.1khz 1.2 e-3 x t ws 1.5 e-3 x t ws ns f ws = 96khz 1.6 e-3 x t ws 2 e-3 x t ws f ws = 192khz 1.6 e-3 x t ws 2e-3 x t ws sck jitter (2-channel i 2 s) tj sck1 t sck = 1/f sck , (cycle-to-cycle), rising-to-rising edge n sck = 16 bits, f ws = 48khz or 44.1khz 13 e-3 x t sck 16 e-3 x t sck ns n sck = 24 bits, f ws = 96khz 39 e-3 x t sck 48 e-3 x t sck n sck = 32 bits, f ws = 192khz 0.1 x t sck 0.13 x t sck ac electrical characteristics (continued) downloaded from: http:///
(v avdd18 = v dvdd18 = 1.7v to 1.9v, v avdd3 = 3.0v to 3.6v, v iovdd = 1.7v to 3.6v, r l = 100 1% (differential), ep connected to pcb ground (gnd), t a = -40c to +105c, unless otherwise noted. typical values are at v avdd18 = v dvdd18 = v iovdd = 1.8v, v avdd3 = 3.3v, t a = +25c.) max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 14 parameter symbol conditions min typ max units sck jitter (8-channel tdm) tj sck2 t sck = 1/f sck , (cycle-to-cycle), rising-to-rising edge n sck = 16 bits, f ws = 48khz or 44.1khz 52 e-3 x t sck 64 e-3 x t sck ns n sck = 24 bits, f ws = 96khz 156 e-3 x t sck 192 e-3 x t sck n sck = 32 bits, f ws = 192khz 0.4 x t sck 0.52 x t sck audio skew relative to video t ask video and audio synchronized 3 x t ws 4 x t ws s sck, sd, ws rise-and-fall time t r , t f 20% to 80% c l = 10pf, dcs = 1 0.3 3.1 ns c l = 5pf, dcs = 0 0.4 3.8 sd, ws valid time before sck (2-channel i 2 s) t dvb1 t sck = 1/f sck , figure 12 0.20 x t sck 0.5 x t sck ns sd, ws valid time after sck (2-channel i 2 s) t dva1 t sck = 1/f sck , figure 12 0.20 x t sck 0.5 x t sck ns sd, ws valid time before sck (8-channel tdm) t dvb2 t sck = 1/f sck , figure 12 0.20 x t sck 0.5 x t sck ns sd, ws valid time after sck (8-channel tdm) t dva2 t sck = 1/f sck , figure 12 0.20 x t sck 0.5 x t sck ns high-speed differentail output ports (dout0_Cdout3_, clk_) (note 10) 20% to 80% rise time and fall time t r , t f bit rate 1gbps 0.3 ui 100 ps data-to-clock skew t skw -0.15 +0.15 ui ui instantaneous ui ins 1 12.5 ns common-level variation above 450mhz v cm 15 mv rms common-level variation between 50mhz to 450mhz 25 mv peak low-speed differential output ports (dout0_Cdout3_, clk_) (note 10) 15% to 85% rise time and fall time t rlp /t flp 25 ns 30% to 85% rise time and fall time transition from hs to lp t reop 35 ns general csi-2 timing specifications (note 10, figure 13) start of transmission: clock prepare time t clk- prepare time that the transmitter drives the clock lane lp-00 line state immediately before hs-0 line state starting the hs transition 38 95 ns ac electrical characteristics (continued) downloaded from: http:///
(v avdd18 = v dvdd18 = 1.7v to 1.9v, v avdd3 = 3.0v to 3.6v, v iovdd = 1.7v to 3.6v, r l = 100 1% (differential), ep connected to pcb ground (gnd), t a = -40c to +105c, unless otherwise noted. typical values are at v avdd18 = v dvdd18 = v iovdd = 1.8v, v avdd3 = 3.3v, t a = +25c.) note 3: limits are 100% production tested at t a = +105c. limits over the operating temperature range are guaranteed by design and characterization, unless otherwise noted. note 4: to provide a mid level, leave the input open, or, if driven, put driver in high impedance. high-imp edance leakage current must be less than 10a. note 5: i in_ min due to voltage drop across the internal pullup resistor. note 6: not production tested. guaranteed by design. note 7: hdcp enabled (max9290 only). iovdd current is not production tested. for the max9288 (or when hdcp is disabled on the max9290), subtract the hdcp supply current, as shown in table 25. note 8: specified pin to ground. note 9: specified pin to all supply/ground. note 10: not production tested, guaranteed by characterization. note 11: measured in serial link bit times. bit time = 1/(30 x f pixel ) for bws = 0 or open. bit time = 1/(40 x f pixel ) for bws = 1. max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 15 parameter symbol conditions min typ max units end of transmission: clock trail time t clk-trail time that the transmitter drives the hs-0 state after the last payload clock bit of a hs transmission burst 60 ns clock start of transmission time t clk- prepare + t clk- zero t clk-prepare + time that the transmitter drives the hs-0 state prior to starting the clock 300 ns clock end of transmission time t eot transmitted time interval from the start of t hs-trail or t clk-trail to start of the lp-11 state following a hs burst 105ns + 12 x ui ns hs exit time t hs-exit time that the transmitter driveslp-11 following a hs burst 100 ns start of transmission: data prepare time t hs- prepare time that the transmitter drives the data lane lp-00 line state immediately before the hs-0 line state starting the hs transmission 40ns + 4 x ui 85ns + 6 x ui ns start of transition time t hs- prepare + t hs- zero t hs-prepare + time that the transmitter drives the hs-0 state prior to transmitting the sync sequence 145ns + 10 x ui ns end of transmission: data trail time t hs-trail time that the transmitter drives the lipped differential state after last payload data bit of a hs transmission burst max(8 x ui, 60ns + 4 x ui) ns lp transmit time t lptx transmitted length of any low-power state period 50 ns ac electrical characteristics (continued) downloaded from: http:///
(v avdd18 = v dvdd18 = v iovdd = 1.8v, v avdd3 = 3.3v, t a = +25c, unless otherwise noted.) max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output maxim integrated 16 www.maximintegrated.com 100 120 140 160 180 200 220 240 260 15 30 45 60 75 90 105 supply current (ma) pclk frequency (mhz) supply current vs. pixel clock frequency (bws = open) toc02 prbs on, coax mode, rgb888, hdcp on 2 channels eq off eq on 100 120 140 160 180 200 220 240 260 5 20 35 50 65 80 supply current (ma) pclk frequency (mhz) supply current vs. pixel clock frequency (bws = high) toc03 prbs on, coax mode, rgb888, hdcp on 2 channels eq off eq on 100 120 140 160 180 200 220 240 260 5 15 25 35 45 55 65 75 85 95 105 supply current (ma) pclk frequency (mhz) supply current vs. pixel clock frequency (bws = low) toc01 prbs on, coax mode, rgb666, hdcp on 2 channels eq off eq on 100 120 140 160 180 200 220 240 260 5 15 25 35 45 55 65 75 85 95 105 supply current (ma) pclk frequency (mhz) supply current vs. pixel clock frequency (bws = low) toc04 prbs on, coax mode, rgb666, hdcp on 4 channels eq off eq on 100 120 140 160 180 200 220 240 260 5 20 35 50 65 80 supply current (ma) pclk frequency (mhz) supply current vs. pixel clock frequency (bws = high) toc06 prbs on, coax mode, rgb888, hdcp on 4 channels eq off eq on 100 120 140 160 180 200 220 240 260 15 30 45 60 75 90 105 supply current (ma) pclk frequency (mhz) supply current vs. pixel clock frequency (bws = open) toc05 prbs on, coax mode, rgb888, hdcp on 4 channels eq off eq on 0 20 40 60 80 100 120 0 5 10 15 20 25 pixel clock frequency (mhz) cable length (m) maximum pixel clock frequency vs. coax cable length (ber 10 - 10 ) toc07 ber can be as low as 10 - 12 for cable lengths less than 15m optimum pe/eq no pe, 10.7db eq no pe/eq typical operating characteristics downloaded from: http:///
(v avdd18 = v dvdd18 = v iovdd = 1.8v, v avdd3 = 3.3v, t a = +25c, unless otherwise noted.) max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output maxim integrated 17 www.maximintegrated.com 100mv/div toc09 2ns/div mipi clock eye pattern 80mbps 100mv/div toc10 200ps/div mipi clock eye pattern 1000mbps 0 20 40 60 80 100 120 0 5 10 15 20 pixel clock frequency (mhz) cable length (m) maximum pixel clock frequency vs. stp cable length (ber 10 -9 ) toc08 ber can be as low as 10 - 12 for cable lengths less than 12m optimum pe/eq no pe, 10.7db eq no pe/eq 6db pe, 10.7db eq 100mv/div toc11 2ns/div mipi data eye pattern 80mbps 500mv/div toc13 50ns/div mipi sot 100mv/div toc12 200ps/div mipi data eye pattern 1000mbps 500mv/div toc14 50ns/div mipi eot typical operating characteristics (continued) downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 18 pin name function 1 intout a/v status register interrupt output. indicates new data in the a/v status registers. intout is rese t when the a/v status registers are read. 2 gpi general-purpose input with internal pulldown to ep. the serializer gpo (or int) output follows gp i. 3 i2csel i 2 c select. control channel interface protocol select input with internal pulldown to ep. set i2csel = high to select i 2 c interface. set i2csel = low to select uart interface. 4 gpio0 open-drain, general-purpose input/output with internal 60k pullup to iovdd 5 bws three-level bus width select input. set bws to the same level on both sides of the serial link. set bws = low for 24 bit mode. set bws = high for 32-bit mode. set bws = open for high-bandwidth mode. 6, 47 avdd3 3.3v analog power supply. bypass avdd3 to ep with 0.1f and 0.001f capacitors as close as possible to the device with the smaller capacitor closest to avdd3. 7 in+ noninverting coax/twisted-pair serial input 8 in- inverting coax/twisted-pair serial input tqfn / qfnd (7 mm x 7 mm x 0 .75mm) connect ep to ground plane ep* max9288 max 9290 top view 13 14 15 16 17 18 19 20 21 22 23 24 rx/sda + tx/scl pwdn ws sck sd add2/cntl2 him/cntl1 iovdd cds dvdd18 rsvd 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 cx/tp avdd3 lmn1 lmn0 lflt iovdd drs err lock add0/cntl0 add1/cntl3 dvdd18 eqs gpio1 dvdd18 ms in- in+ avdd3 bws gpio0 i2csel gpi intout 36 35 34 33 32 31 30 29 28 27 26 25 avdd18 dout3+ dout3- dout2+ dout2- clk+ clk- dout1+ dout1- dout0+ dout0- avdd18 pin description pin coniguration downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 19 pin name function 9 ms mode select with internal pulldown to ep. ms sets the control-link mode when cds = high. set ms = low, to select base mode. set ms = high to select the bypass mode. ms sets autostart mode when cds = low. 10, 23, 37 dvdd18 1.8v digital power supply. bypass dvdd18 to ep with 0.1f and 0.001f capacitors as close as possible to the device with the smaller value capacitor closest to dvdd18. 11 gpio1 open-drain, general-purpose input/output with internal 60k pullup to iovdd 12 eqs equalizer select input with internal pulldown to ep. the state of eqs latches upon power-up or when resuming from power-down mode ( pwdn = low). leave eqs open for 10.7db equalizer boost (eqtune = 1001). connect eqs to iovdd with a 30k resistor for 5.2db equalizer boost (eqtune = 0100). 13 rx/sda uart receive/i 2 c serial data input/output with internal 30k pullup to iovdd. function is determined by the state of i2csel at power-up. rx/sda has an open-drain driver and requires a pullup resistor. rx: input of the deserializers uart. sda: data input/output of the deserializers i 2 c master/slave. 14 tx/scl uart transmit/i 2 c serial clock input/output with internal 30k pullup to iovdd. function is determined by the state of i2csel at power-up. tx/scl has an open-drain driver and requires a pullup resistor. tx: output of the deserializers uart. scl: clock input/output of the deserializers i 2 c master/slave. 15 pwdn active-low, power-down input with internal pulldown to ep. set pwdn low to enter power-down mode to reduce power consumption. 16 ws i 2 s/tdm word-select input/output. powers up as an i 2 s output (deserializer provided clock). set audiomode bit = 1 to change ws to an input with internal pulldown to gnd and supply ws externally (system provided clock). 17 sck i 2 s/tdm serial-clock input/output. powers up as an i 2 s output (deserializer provided clock). set audiomode bit = 1 to change sck to an input with internal pulldown to gnd and supply sck externally (system provided clock). 18 sd i 2 s/tdm serial-data output. disable i 2 s/tdm encoding to serial data to use sd as an additional control/data output. encrypted when hdcp is enabled. 19 add2/cntl2 address selection input/auxiliary control signal output with internal pulldown to ep. functions as add2 input at power-up or when resuming from power-down mode ( pwdn = low), and switches to cntl2 output automatically after power-up.add2: bit value is latched at power-up or when resuming from power-down mode ( pwdn = low). see table 1. connect add2/cntl2 to iovdd with a 30k resistor to set high or leave open to set low. cntl2: used only in 32-bit and high-bandwidth mode (bws = high, open). cntl2 is mapped from the gmsl serializers cntl2 or din28 input. pin description (continued) downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 20 pin name function 20 him/cntl1 high-immunity mode input/auxiliary control signal output with internal pulldown to ep. functions as him input at power-up or when resuming from power-down mode ( pwdn = low), and switches to cntl2 output automatically after power-up.him: default highimm bit value is latched at power-up or when resuming from power-down mode ( pwdn = low) and is active-high. connect him/cntl1 to iovdd with a 30k resistor to set high or leave open to set low. highimm can be programmed to a different value after power-up. highimm in the serializer must be set to the same value. cntl1: used only in 32-bit and high-bandwidth mode (bws = high, open). cntl1 is mapped from the gmsl serializers cntl1, din27, or res input. 21, 43 iovdd i/o supply voltage. 1.8v to 3.3v logic i/o power supply. bypass iovdd to ep with 0.1f and 0.001f capacitors as close as possible to the device with the smallest value capacitor closest to iovdd. 22 cds control direction selection input with internal pulldown to ep. control link direct selection input with internal pulldown to ep. set cds = low when the control channel master c is connected at the serializer. set cds = high when the control channel master c is connected at the deserializer. 24 res reserved. leave unconnected 25, 36 avdd18 1.8v analog power supply. bypass avdd18 to ep with 0.1f and 0.001f capacitors as close as possible to the device with the smaller capacitor closest to avdd18. 26C29, 32C35 dout_+, dout_- csi-2 data outputs 30, 31 clk+, clk- csi-2 clock output 38 add1/cntl3 auxiliary control signal output/address selection input with internal pulldown to ep. functions as add1 input at power-up or when resuming from power-down mode ( pwdn = low), and switches to cntl3 output automatically after power-up.add1: bit value is latched at power-up or when resuming from power-down mode ( pwdn = low). see table 1. connect add1/cntl3 to iovdd with a 30k resistor to set high or leave open to set low. cntl3: used only in high-bandwidth mode (bws = open. 39 add0/cntl0 auxiliary control signal output/address selection input with internal pulldown to ep. functions as add0 input at power-up or when resuming from power-down mode ( pwdn = low), and switches to cntl0 output automatically after power-up.add0: bit value is latched at power-up or when resuming from power-down mode ( pwdn = low). see table 1. connect add0/cntl0 to iovdd with a 30k resistor to set high or leave open to set low. cntl0: used only in high-bandwidth mode (bws = open). 40 lock open-drain lock output with internal 60k pullup to iovdd. lock = high indicates that plls are locked with correct serial-word-boundary alignment. lock = low indicates that plls are not locked or an incorrect serial-word-boundary alignment. lock is high when pwdn = low. pin description (continued) downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 21 pin name function 41 err error output. open-drain data error detection and/or correction indication output with internal 60k pullup to iovdd. err is high when pwdn is low. 42 drs data-rate select input is latched upon power-up or when pwdn transitions low-to-high. set drs high for pixel clock rates below 16.66mhz (bws = low), 12.5mhz (bws = high), or 36.66mhz (bws = open). set drs = low for faster pixel clock rates. 44 lflt active-low open-drain line-fault output. lflt has a 60k internal pullup to iovdd. lflt = low indicates a line fault. lflt is high when pwdn = low. 45 lmn0 line fault monitor input 0 (see figure 1) 46 lmn1 line fault monitor input 1 (see figure 1) 48 cx/tp three-level coax/twisted pair select input. see table 12 for function. ep exposed pad. ep is internally connected to device ground. must connect ep to the pcb ground plane through an array of vias for proper thermal and electrical performance. serial to parallel fifo parallel to csi-2 i 2 s/tdm tx rgb vs de hs rgb cntl[3:0] (9b10b) clk dout0 dout1 dout2 dout3 pwdn bws reverse control channel video max9288 max 9290 in+ in- clkdiv hdcp decrypt vs de hs hdcp decrypt hdcp keys cdrpll hdcp control fcc acb sd/him ws sck cml rx and eq add[2:0] 8b/10b decode/ descramble (max9290 only) control (9b10b) sync uart/i 2 c tx/ scl rx/ sda gpio_ gpi i2csel add0/cntl0, him/cntl1, add2/cntl2, add1/cntl3 data description registers intout control cx/tp add[2:0], him cds eqs ms pll pin description (continued) functional diagram downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 22 figure 1. line fault output logic (in+) output logic (in-) reference voltage generator gmsl deserializer max9288/max9290 gmsl deserializer twisted pair connectors *1% tolerance lflt lmn0 1.8v lmn1 49.9k ? * 49.9k ? * lmn1in+ in- 4.99k ? * 45.3k ? * 45.3k ? * 4.99k ? * lmn0 gmsl deserializer coax connectors 1.8v 49.9k ? * in+in- 45.3k ? * lmn0 4.99k ? * 49.9 ? * downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 23 figure 2. reverse control-channel output parameters figure 3. test circuit for differential input measurement v in+ r l /2 r l /2 c in c in v id(p) in+ in- v id(p) = | v in+ - v in- | v cmr = (v in+ + v in- )/2 v in- _ + _ _ + c in 0.22 f 49.9 ? + - v in_ in_ v is(p) max9288max9290 reverse control-channel transmitter in+ in- in- in+ in+ in- v od r l /2 r l /2 v cmr v cmr v roh (in+) - (in-) t r 0.1 x v rol 0.9 x v rol t f v rol 0.9 x v roh 0.1 x v roh figure 4. test circuit for single-ended input measurement downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 24 figure 5. worst-case pattern outputfigure 6. i 2 c timing parameters vs 2 de/hs 3 din_ (even inputs) 1. gmsl serializer input signal 2. vs starts low and remains high 3. register setting determines if de or hs is used din_ (odd inputs) signal 1 2000 pclk cycles pclkin 200 pclk cycles 200 pclk cycles 2000 pclk cycles protocol scl sda start condition (s) bit 7 msb (a7) bit 6 (a6) bit 0 (r/w) acknowledge (a) stop condition (p) v iovdd x 0.7 v iovdd x 0.3 v iovdd x 0.7 v iovdd x 0.3 t su;sta t low t high t buf t hd;sta t r t sp t f t su;dat t hd;dat t vd;dat t vd;ack t su;sto 1/f scl downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 25 figure 7. output rise-and-fall times figure 8. deserializer delay 0.8 x v i0vdd 0.2 x v i0vdd t f t r c l single-ended output load serial word n (first pixel word of a line) serial byte n, n+1, n+2 last bit first bit serial word n+2 serial word n +1 serial word length t sd txdout+ txdout- downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 26 figure 10. lock time figure 11. power-up delay figure 12. output i 2 s timing parameters figure 9. gpi-to-gpo delay ws t dva t dvb t dva t f t dvb t r sck sd in+, in-lock t lock pwdn must be high v oh in+, in- lock t pu pwdn v oh v ih1 t gpio t gpio v oh_min v ol_max v ih_min v il_max deserializer gpi serializer gpo downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 27 detailed description the max9288/max9290 deserializers, when paired with the max9275/max9277/max9279/max9281 serializ - ers, provide the full set of operating features, but are backward-compatible with the max9249Cmax9270 fam- ily of gigabit multimedia serial link (gmsl) devices, and have basic functionality when paired with any gmsl device. the max9290 has high-bandwidth digital content protection (hdcp), while the max9288 does not. each deserializer has a maximum serial-bit rate of 3.12gbps for up to 15m of cable and operates up to a maximum output clock of 104mhz in 24-bit mode and 27-bit high-bandwidth mode, or 78mhz in 32-bit mode. this bit rate and output flexibility support a wide range of displays, from qvga (320 x 240) to 1920 x 720 and higher with 24-bit color, as well as megapixel image sen- sors. an encoded audio channel supports l-pcm i 2 s stereo and up to eight channels of l-pcm in tdm mode. sample rates of 32khz to 192khz are supported with sample depth from 8 to 32 bits. input equalization, com- bined with gmsl serializer pre/deemphasis, extends the cable length and enhances link reliability. the control channel enables a c to program the serial- izer and deserializer registers and program registers on peripherals. the control channel is also used to perform hdcp functions (max9290 only). the c can be located at either end of the link, or when using two cs, at both ends. two modes of control-channel operation are avail- able. base mode uses either i 2 c or gmsl uart protocol, while bypass mode uses a user-defined uart protocol. uart protocol allows full-duplex communication, while i 2 c allows half-duplex communication. the serial input complies with iso 10605 and iec 61000- 4-2 esd protection standards. register mapping registers set the operating conditions of the deserial- izers and are programmed using the control channel in base mode. the max9288/max9290 holds its own device address and the device address of the serial - izer it is paired with. similarly, the serializer holds its own device address and the address of the max9288/ max9290. whenever a device address is changed, be sure to write the new address to both devices. the default device address of the deserializer is set by the add_ and cx/tp inputs ( table 1 ). registers 0x00 and 0x01 in both devices hold the device addresses. figure 13. mipi output timing parameters clk+/- dout_+/- v il(max) v ih(min) v idth(max) capture 1 st data bit t lptx t hs-prepare t hs-zero t hs-sync lp-11 lp-01 lp-00 t d-term-en t hs-settle lp-11 t hs-skip t reot t eot t hs-trail t hs-exit disconnect terminator v term-en(max) clk+/- v il(max) v idth(max) t lptx t clk-prepare t clk-zero lp-11 lp-01 lp-00 t d-term-en t hs-settle v term-en(max) note: the csi clock runs in continuous mode only. downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 28 output bit map the input/output bit width depends on settings of the bus width pin (bws) and the csi-2 output mode. table 4 and table 3 list the bit map for video signals. table 4 lists the bit map for control signals. unused control output bits are pulled low. serial link signaling and data format the serializer uses differential cml signaling to drive twisted-pair cable and single-ended cml to drive coaxial cable with programmable pre/deemphasis and ac-coupling. the deserializer uses ac-coupling and programmable channel equalization. input data is scrambled and then 8b/10b coded (9b/10b in high-bandwidth mode). the deserializer recovers the embedded serial clock, then samples, decodes, and descrambles the data. in 24-bit mode, the first 21 bits contain 18 bits of video data and 3 bits of control data (hs/vs/de). in 32-bit mode, the first 29 bits contain 24 bits of video data, 3 bits of control data (hs/vs/de) and two bits of control data (cntl1/cntl2). in high- bandwidth mode, the first 24 bits contain video data, or special control-signal packets. in all modes, the last 3 bits contain the embedded audio channel, the embedded for- ward control channel, and the parity bit of the serial word ( figure 14 , figure 15 , figure 16 ). gmsl-to-csi-2 conversion and output the gmsl deserializer recovers the clock from the serialized input signals and extracts the video, audio, and control. video data are packetized to according to mipi csi-2 packet formats and sent out through the mipi dphy serial lanes. video data operation the device converts the video control signal vs to the csi-2 frame start or frame end short packet ( figure 17 ). the converter also assembles the pixel color data into the csi-2 long packets based on the formats and/or pixel count programmed by the user ( figure 18 , figure 19 , figure 20 , figure 21 , figure 22 , figure 23 , figure 24 , figure 25 , figure 26 , figure 27 , figure 28 , figure 29 , figure 30 , and figure 31 ). de low period needs to be a minimum 200 pclk cycles to accommodate sot and eot during the de blanking period. table 1. device address defaults (register 0x00, 0x01) *x = 0 for the serializer address, x = 1 for the deserializer address. **cx/tp determine the serial-cable type cx/tp = open addresses only for coax mode. pin device address (bin) serializer device address (hex) deserializer device address (hex) cx/tp add2 add1 add0 d7 d6 d5 d4 d3 d2 d1 d0 high/low low low low 1 0 0 x* 0 0 0 r/ w 80 90 high/low low low high 1 0 0 x* 0 1 0 r/ w 84 94 high/low low high low 1 0 0 x* 1 0 0 r/ w 88 98 high/low low high high 0 1 0 x* 0 1 0 r/ w 44 54 high/low high low low 1 1 0 x* 0 0 0 r/ w c0 d0 high/low high low high 1 1 0 x* 0 1 0 r/ w c4 d4 high/low high high low 1 1 0 x* 1 0 0 r/ w c8 d8 high/low high high high 0 1 0 x* 1 0 0 r/ w 48 58 open** low low low 1 0 0 x* 0 0 x* r/ w 80 92 open** low low high 1 0 0 x* 0 1 x* r/ w 84 96 open** low high low 1 0 0 x* 1 0 x* r/ w 88 9a open** low high high 0 1 0 x* 0 1 x* r/ w 44 56 open** high low low 1 1 0 x* 0 0 x* r/ w c0 d2 open** high low high 1 1 0 x* 0 1 x* r/ w c4 d6 open** high high low 1 1 0 x* 1 0 x* r/ w c8 da open** high high high 0 1 0 x* 1 0 x* r/ w 48 5a downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 29 figure 14. 24-bit mode serial data formatfigure 15. 32-bit mode serial data format packet parity check bit acb fcc pcb d0 d1 hs vs de d20 d19 d18 d17 de/vs/hs must be set at dout[20:18] max 9290 note: only dout[17:0] and audio have hdcp encryption. video data (to csi-2) control bits (to csi-2) dout0 dout1 dout17 dout18/ hs dout19/ vs dout20/ de serial data internal parallel bit ws sck sd rx/ sda tx/scl audio decode i 2 s/tdm audio uart/i 2 c forward control- channel bit 24 bits de/vs/hs must be set at dout[20:18]. max 9290 note: only dout[17:0], dout[26:21], and audio have hdcp encryption. d23 32 bits packet parity check bit d24 d25 d26 d27 d28 acb fcc pcb d0 d1 hs vs de d22 d21 d20 d19 d18 d17 video data (to csi-2) control bits (to csi-2) video data (to csi-2) aux control bits dout 0 dout 1 dout 17 dout 18/hs dout 19/vs dout 20/de dout 21 dout 22 dout 23 dout 24 dout 25 dout 26 cntl1 cntl2 serial data internal parallel bit ws sck sd rx/ sda tx/ scl audio decode i 2 s/tdm audio uart/i 2 c forward control- channel bit downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 30 figure 16. high-bandwidth mode serial-data format figure 17. transmitting a frame from gmsl to mipi d0 serial data d1 27 bits input pin dout 0 dout 1 d17 d18 d19 d20 d21 d22 d23 acb fcc pcb dout 17 dout 21 dout 22 dout 23 dout 24 dout 25 dout 26 ws sck sd rx/ sda tx/ scl input signal r0 r1 b5 r6 r7 g6 g7 b6 b7 hs vs de rgb data rgb data i 2 s/tdm audio uart/i 2 c vs/hs must be set at dout[20:18]. max9290 note: only dout[17:0], dout[26:21] and acb have hdcp encryption. audio decode forward control- channel bit packet parity check bit special serial-data packet cntl0/ add0 dout27/ cntl1 dout28/ cntl2 cntl3 add1 dout 18/hs dout 19/vs dout 20/de aux control bits control bits control-signal decoding 27 bits vs de* dout csi-2 dout_ hs* key: sot: start of transmission eot: end of transmission ph: packet header pf: packet footer fs: frame start fe: frame end lps: low power state sot fs eot lps lps sot fe eot lps lps lpkt spkt lpkt spkt sot ph eot lps lps data pf *register setting determines whether de or hs is used for packet timing 200pclk 200pclk 200pclk 200pclk 200pclk downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 31 figure 18. rgb565 output vs de dout0 dout1 dout18 /hs dout19 /vs dout20 /de dout21 dout26 gmsl parallel bit r-0 r-1 r-4 dout4 dout5 dout6 dout10 dout11 dout12 dout15 g-0 g-1 g-5 b-0 b-1 b-4 gmsl to csi-2 rgb565 b2[4:0] packet header r2[4:0] b(n-1)[4:0] r(n-1)[4:0] b(n)[4:0] r(n)[4:0] g(n)[5:0] packet footer data id word count ecc b-0 b-1 b-2 b-3 b-4 g-0 g-1 g-2 r-0 r-1 r-2 r-3 r-4 g-3 g-4 g-5 8 bits 16 bits 8 bits d7 0 d6 0 d5 dt5 d4 dt4 d3 dt3 d2 dt2 d1 dt1 d0 dt0 d7 vc1 d6 vc0 d5 dt5 d4 dt4 d3 dt3 d2 dt2 d1 dt1 d0 dt0 crc ls byte crc ms byte data type 0x00 C 0x07 0x08 C 0x0f 0x10 C 0x17 0x18 C 0x1f 0x30 C 0x37 0x38 C 0x3f 0x20 C 0x27 0x28 C 0x2f description synchronization short packet data types generic short packet data types generic long packet data types (type 0x12 used for embedded audio yuv data user defined byte based data reserved rgb data raw data 1 of 4 channel select data type select 8 bits 8 bits word count pixel bytes bits 1 2 16 line start line stop res res dout16 dout17 res res no input when bws = low b1[4:0] r1[4:0] n 2n controls fs & fe and packet start/end g(n-1)[5:0] g2[5:0] g1[5:0] wrd 1 wrd 2 wrd 3 wrd 4 word (wc C 2) word (wc -1) word wc word (wc C 3) msb lsb msb lsb msb lsb hs downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 32 figure 19. rgb666 output controls fs & fe and packet start/end dout0 dout1 dout18 /hs dout19 /vs dout20 /de dout21 dout26 gmsl parallel bit dout5 dout6 dout7 dout11 dout12 dout13 dout17 gmsl to csi-2 rgb666 b2[5:0] packet header r2[5:0] g2[5:0] b1[5:0] r1[5:0] g1[5:0] b(n-1)[5:0] r(n-1)[5:0] g(n-1)[5:0] b(n)[5:0] r(n)[5:0] g(n)[5:0] packet footer data id word count ecc b-0 b-1 b-2 b-3 b-4 b-5 g-0 g-1 g-2 g-3 g-4 g-5 r-0 r-1 r-2 r-3 r-4 r-5 8 bits 16 bits 8 bits d7 0 d6 0 d5 dt5 d4 dt4 d3 dt3 d2 dt2 d1 dt1 d0 dt0 d7 vc1 d6 vc0 d5 dt5 d4 dt4 d3 dt3 d2 dt2 d1 dt1 d0 dt0 crc ls byte crc ms byte data type 0x00 C 0x07 0x08 C 0x0f 0x10 C 0x17 0x18 C 0x1f 0x30 C 0x37 0x38 C 0x3f 0x20 C 0x27 0x28 C 0x2f description synchronization short packet data types generic short packet data types generic long packet data types (type 0x12 used for embedded audio yuv data user defined byte based data reserved rgb data raw data 1 of 4 channel select data type select 8 bits 8 bits word count pixel bytes bits 1 2.25 18 line start line stop hs vs de r-0 r-1 r-4 g-0 g-1 g-5 b-0 b-1 b-4 res res *pixel count needs to be a multiple of 4 word 1 word 2 word 3 word 4 word (wc) - 2 word (wc) -1 word wc word (wc) - 3 n* 9/4 x n msb lsb msb lsb msb lsb downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 33 figure 20. rgb888 output hs vs de controls fs & fe and packet start/end dout0 dout1 dout18 /hs dout19 /vs dout20 /de dout21 dout22 dout23 dout24 dout25 dout26 gmsl parallel bit* r-0 r-1 r-5 dout5 dout6 dout7 dout11 dout12 dout13 dout17 g-0 g-1 g-5 b-0 b-1 b-5 r-6 r-7 g-6 g-7 b-6 b-7 gmsl to csi-2 rgb888 (bws = high or open) b1[7:0] packet header r1[7:0] g1[7:0] b2[7:0] r2[7:0] g2[7:0] b(n-1)[7:0] r(n-1)[7:0] g(n-1)[7:0] b(n)[7:0] r(n)[7:0] g(n)[7:0] packet footer data id word count ecc d0 b-0 d1 b-1 d2 b-2 d3 b-3 d4 b-4 d5 b-5 d6 b-6 d7 b-7 8 bits 16 bits 8 bits d7 0 d6 0 d5 dt5 d4 dt4 d3 dt3 d2 dt2 d1 dt1 d0 dt0 d7 vc1 d6 vc0 d5 dt5 d4 dt4 d3 dt3 d2 dt2 d1 dt1 d0 dt0 crc ls byte crc ms byte data type 0x00 C 0x07 0x08 C 0x0f 0x10 C 0x17 0x18 C 0x1f 0x30 C 0x37 0x38 C 0x3f 0x20 C 0x27 0x28 C 0x2f description synchronization short packet data types generic short packet data types generic long packet data types (type 0x12 used for embedded audio yuv data user defined byte based data reserved rgb data raw data 1 of 4 channel select data type select 8 bits 8 bits line start line stop wrd 1 wrd 2 wrd 3 wrd 4 wrd wc- 2 wrd wc -1 wrd wc wrd wc - 4 wrd 5 wrd 6 wrd wc - 5 wrd wc - 3 d0 g-0 d1 g-1 d2 g-2 d3 g-3 d4 g-4 d5 g-5 d6 g-6 d7 g-7 d0 r-0 d1 r-1 d2 r-2 d3 r-3 d4 r-4 d5 r-5 d6 r-6 d7 r-7 *vesa and oldi define naming conventions with regards to msb and lsb. the gmsl to mipi mapping is shown in the table to the right. word count pixel bytes bits 1 3 24 n 3n oldi = 0 (vesa) r7 (msb) r6 r5 oldi = 1 (odli) r4 r3 r2 r1 r0 (lsb) r7 r4 r5 (msb) r3 r2 r1 r6 (lsb) r0 gmsl bit name mipi bit name r1 r7 (msb) r5 r4 r3 r0 (lsb) r2 r6 downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 34 figure 21. yuv422 8-bit (muxed) output dout0 dout1 cb-0 cb-1 cb-7 dout7 dout8 gmsl to csi-2 yuv422 8 bit (muxed) y2[7:0] packet header cb1[7:0] cr2[7:0] y1[7:0] cb(n-1)[7:0] y(n-1)[7:0] y(n)[7:0] cr(n)[7:0] packet footer data id word count ecc 8 bits 16 bits 8 bits d7 0 d6 0 d5 dt5 d4 dt4 d3 dt3 d2 dt2 d1 dt1 d0 dt0 d7 vc1 d6 vc0 d5 dt5 d4 dt4 d3 dt3 d2 dt2 d1 dt1 d0 dt0 crc ls byte crc ms byte data type 0x00 C 0x07 0x08 C 0x0f 0x10 C 0x17 0x18 C 0x1f 0x30 C 0x37 0x38 C 0x3f 0x20 C 0x27 0x28 C 0x2f description synchronization short packet data types generic short packet data types generic long packet data types (type 0x12 used for embedded audio yuv data user defined byte based data reserved rgb data raw data 1 of 4 channel select data type select 8 bits 8 bits word count pixel bytes bits 1 2 16 line start line stop n 2n wrd wc- 2 wrd wc -1 wrd wc wrd wc - 3 hs vs de dout18 /hs dout19 /vs dout20 /de dout21 dout26 res res dout17 res no input when bws = low dout0 dout1 cr-0 cr-1 cr-7 dout7 dout8 hs vs de dout18 /hs dout19 /vs dout20 /de dout21 dout26 res res dout17 res controls fs & fe and packet start/end dout0 dout1 dout7 dout8 hs vs de dout18 /hs dout19 /vs dout20 /de dout21 dout26 res res dout17 res dout0 dout1 dout7 dout8 y-0 y-1 y-7 hs vs de dout18 /hs dout19 /vs dout20 /de dout21 dout26 res res dout17 res y-0 y-1 y-7 res res res res d7 cb-7 d6 cb-6 d5 cb-5 d4 cb-4 d3 cb-3 d2 cb-2 d1 cb-1 d0 cb-0 d7 y-7 d6 y-6 d5 y-5 d4 y-4 d3 y-3 d2 y-2 d1 y-1 d0 y-0 d7 cr-7 d6 cr-6 d5 cr-5 d4 cr-4 d3 cr-3 d2 cr-2 d1 cr-1 d0 cr-0 wrd 1 wrd 2 wrd 3 wrd 4 downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 35 figure 22. yuv422 10-bit (muxed) output dout0 dout1 cb-0 cb-1 cb-2 dout2 dout10 gmsl to csi-2 yuv422 10 bit (muxed) y2[9:2] packet header cb1[9:2] cr2[9:2] y1[9:2] cb(n-1)[9:2] y(n-1)[9:2] y(n)[9:2] cr(n)[9:2] packet footer data id word count ecc 8 bits 16 bits 8 bits d7 0 d6 0 d5 dt5 d4 dt4 d3 dt3 d2 dt2 d1 dt1 d0 dt0 d7 vc1 d6 vc0 d5 dt5 d4 dt4 d3 dt3 d2 dt2 d1 dt1 d0 dt0 crc ls byte crc ms byte data type 0x00 C 0x07 0x08 C 0x0f 0x10 C 0x17 0x18 C 0x1f 0x30 C 0x37 0x38 C 0x3f 0x20 C 0x27 0x28 C 0x2f description synchronization short packet data types generic short packet data types generic long packet data types (type 0x12 used for embedded audio yuv data user defined byte based data reserved rgb data raw data 1 of 4 channel select data type select 8 bits 8 bits word count pixel bytes bits 1 2.5 20 line start line stop n* 2.5n wrd wc- 2 wrd wc -1 wrd wc wrd wc - 3 hs vs de dout18 /hs dout19 /vs dout20 /de dout21 dout26 res res dout17 res no input when bws = low dout0 dout1 cr-0 cr-1 cr-2 dout2 dout10 hs vs de dout18 /hs dout19 /vs dout20 /de dout21 dout26 res res dout17 res controls fs & fe and packet start/end dout2 dout10 hs vs de dout18 /hs dout19 /vs dout20 /de dout21 dout26 res res dout17 res dout2 dout10 y-0 y-1 y-2 hs vs de dout18 /hs dout19 /vs dout20 /de dout21 dout26 res res dout17 res y-2 res res res res dout9 cb-9 dout9 cr-9 dout9 dout9 y-9 y-9 lsb lsb wrd wc - 4 *pixel count needs to be a multiple of 2 y-8 y-9 y-2 y-3 y-4 y-5 y-6 y-7 d6 cr-8 d7 cr-9 d0 cr-2 d1 cr-3 d2 cr-4 d3 cr-5 d4 cr-6 d5 cr-7 cb-8 cb-9 cb-2 cb-3 cb-4 cb-5 cb-6 cb-7 d6 y2-0 d7 y2-1 d4 cr2-0 d5 cr2-1 d2 y1-0 d3 y1-1 d0 cb1-0 d1 cb1-1 y-0 y-1 wrd 1 wrd 2 wrd 3 wrd 4 wrd 5 dout0 dout1 dout0 dout1 downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 36 figure 23. yuv422 8-bit output dout 0 dout 1 cb-0 cb-1 cb-7 dout 7 dout 8 dout 9 dout 15 y-0 y-1 y-7 gmsl to csi-2 yuv422 8 bit y2[7:0] packet header cb1[7:0] cr2[7:0] y1[7:0] cb(n-1)[7:0] y(n-1)[7:0] y(n)[7:0] cr(n)[7:0] packet footer data id word count ecc 8 bits 16 bits 8 bits d7 0 d6 0 d5 dt5 d4 dt4 d3 dt3 d2 dt2 d1 dt1 d0 dt0 d7 vc1 d6 vc0 d5 dt5 d4 dt4 d3 dt3 d2 dt2 d1 dt1 d0 dt0 crc ls byte crc ms byte data type 0x00 C 0x07 0x08 C 0x0f 0x10 C 0x17 0x18 C 0x1f 0x30 C 0x37 0x38 C 0x3f 0x20 C 0x27 0x28 C 0x2f description synchronization short packet data types generic short packet data types generic long packet data types (type 0x12 used for embedded audio yuv data user defined byte based data reserved rgb data raw data 1 of 4 channel select data type select 8 bits 8 bits word count pixel bytes bits 1 2 16 line start line stop n 2n wrd wc- 2 wrd wc -1 wrd wc wrd wc - 3 hs vs de dout 18/hs dout 19/vs dout 20/de dout 21 dout 26 res res dout 16 dout 17 res res no input when bws = low dout 0 dout 1 cr-0 cr-1 cr-7 dout 7 dout 8 dout 9 dout 15 y-0 y-1 y-7 hs vs de dout 18/hs dout 19/vs dout 20/de dout 21 dout 26 res res dout 16 dout 17 res res controls fs & fe and packet start/end d7 cb-7 d6 cb-6 d5 cb-5 d4 cb-4 d3 cb-3 d2 cb-2 d1 cb-1 d0 cb-0 d7 cr-7 d6 cr-6 d5 cr-5 d4 cr-4 d3 cr-3 d2 cr-2 d1 cr-1 d0 cr-0 d7 y-7 d6 y-6 d5 y-5 d4 y-4 d3 y-3 d2 y-2 d1 y-1 d0 y-0 wrd 1 wrd 2 wrd 3 wrd 4 downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 37 figure 24. yuv422 10-bit output dout 0 dout 1 cb-0 cb-1 cb-2 dout 2 gmsl to csi-2 yuv422 10 bit (bws = high or open) y2[9:2] packet header cb1[9:2] cr2[9:2] y1[9:2] cb(n-1)[9:2] y(n-1)[9:2] y(n)[9:2] cr(n)[9:2] packet footer data id word count ecc d6 y2-0 d7 y2-1 d4 cr2-0 d5 cr2-1 d2 y1-0 d3 y1-1 d0 cb1-0 d1 cb1-1 8 bits 16 bits 8 bits d7 0 d6 0 d5 dt5 d4 dt4 d3 dt3 d2 dt2 d1 dt1 d0 dt0 d7 vc1 d6 vc0 d5 dt5 d4 dt4 d3 dt3 d2 dt2 d1 dt1 d0 dt0 crc ls byte crc ms byte data type 0x00 C 0x07 0x08 C 0x0f 0x10 C 0x17 0x18 C 0x1f 0x30 C 0x37 0x38 C 0x3f 0x20 C 0x27 0x28 C 0x2f description synchronization short packet data types generic short packet data types generic long packet data types (type 0x12 used for embedded audio yuv data user defined byte based data reserved rgb data raw data 1 of 4 channel select data type select 8 bits 8 bits word count pixel bytes bits 1 2.5 20 line start line stop n* 2.5n wrd wc- 2 wrd wc -1 wrd wc wrd wc - 3 hs vs de dout 18/hs dout 19/vs dout 20/de dout 23 dout 26 res res cr-0 cr-1 cr-2 controls fs & fe and packet start/end dout 10 dout 11 dout 12 hs vs de dout 18/hs dout 19/vs dout 20/de dout 0 dout 1 dout 2 y-0 y-1 y-2 dout 9 cb-9 cr-9 dout 17 dout 9 y-7 lsb lsb wrd wc - 4 *pixel count needs to be a multiple of 2 dout 21 y-8 dout 22 y-9 y-0 y-1 y-2 y-7 dout 10 dout 11 dout 12 dout 17 dout 23 dout 26 res res dout 21 y-8 dout 22 y-9 y-8 y-9 y-2 y-3 y-4 y-5 y-6 y-7 d6 cr-8 d7 cr-9 d0 cr-2 d1 cr-3 d2 cr-4 d3 cr-5 d4 cr-6 d5 cr-7 cb-8 cb-9 cb-2 cb-3 cb-4 cb-5 cb-6 cb-7 wrd 1 wrd 2 wrd 3 wrd 4 wrd 5 downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 38 figure 25. yuv422 12-bit output dout0 dout1 cb-0 cb-1 cb-2 dout2 gmsl to csi-2 yuv422 12 bit (user defined, bws = high or open) y2[11:4] packet header cb1[11:4] cr2[11:4] y1[11:4] cb(n-1)[11:4] y(n-1)[11:4] y(n)[11:4] cr(n)[11:4] packet footer data id word count ecc d7 cb-3 d6 cb-2 d3 y-3 d2 y-2 8 bits 16 bits 8 bits d7 0 d6 0 d5 dt5 d4 dt4 d3 dt3 d2 dt2 d1 dt1 d0 dt0 d7 vc1 d6 vc0 d5 dt5 d4 dt4 d3 dt3 d2 dt2 d1 dt1 d0 dt0 crc ls byte crc ms byte data type 0x00 C 0x07 0x08 C 0x0f 0x10 C 0x17 0x18 C 0x1f 0x30 C 0x37 0x38 C 0x3f 0x20 C 0x27 0x28 C 0x2f description synchronization short packet data types generic short packet data types generic long packet data types (type 0x12 used for embedded audio yuv data yuv 422 12-bit = 0x30 reserved rgb data raw data 1 of 4 channel select data type select 8 bits 8 bits word count pixel bytes bits 1 3 24 line start line stop n 3n wrd wc- 2 wrd wc -1 wc wc - 3 cb-8 cb-9 cb-10 cb-11 cb-4 cb-5 cb-6 cb-7 hs vs de dout18 /hs dout19 /vs dout20 /de dout26 controls fs & fe and packet start/end dout12 dout13 dout14 y-0 y-1 y-2 dout11 cb-11 dout17 y-5 lsb wrd wc- 4 dout21 y-6 dout3 cb-3 cb-4 dout4 dout15 dout16 y-3 y-4 y-11 dout0 dout1 cr-0 cr-1 cr-2 dout2 hs vs de dout18 /hs dout19 /vs dout20 /de dout26 dout12 dout13 dout14 y-0 y-1 y-2 dout11 cr-11 dout17 y-5 dout21 y-6 dout3 cr-3 cr-4 dout4 dout15 dout16 y-3 y-4 y-11 lsb lsb lsb wrd wc - 4 d5 cb-1 d4 cb-0 d1 y-1 d0 y-0 y-8 y-9 y-10 y-11 y-4 y-5 y-6 y-7 d4 cr-8 d5 cr-9 d6 cr-10 d7 cr-11 d0 cr-4 d1 cr-5 d2 cr-6 d3 cr-7 d7 cr-3 d6 cr-2 d3 y-3 d2 y-2 d5 cr-1 d4 cr-0 d1 y-1 d0 y-0 wrd 1 wrd 2 wrd 3 wrd 4 wrd 5 wrd 6 downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 39 figure 26. raw 8-bit (double load) output hs vs de controls fs & fe and packet start/end dout0 dout1 dout18 /hs dout19 /vs dout20 /de gmsl parallel bit pa-0 pa-1 pa-7 dout7 dout8 dout9 dout15 dout16 dout17 pb-0 pb-1 pb-7 gmsl to csi-2 raw 8 bit (double load) packet header p1[7:0] p2[7:0] p(n-3)[7:0] p(n-2)[7:0] p(n)[7:0] p(n-1)[7:0] packet footer data id word count ecc 8 bits 16 bits 8 bits d7 0 d6 0 d5 dt5 d4 dt4 d3 dt3 d2 dt2 d1 dt1 d0 dt0 d7 vc1 d6 vc0 d5 dt5 d4 dt4 d3 dt3 d2 dt2 d1 dt1 d0 dt0 crc ls byte crc ms byte data type 0x00 C 0x07 0x08 C 0x0f 0x10 C 0x17 0x18 C 0x1f 0x30 C 0x37 0x38 C 0x3f 0x20 C 0x27 0x28 C 0x2f description synchronization short packet data types generic short packet data types generic long packet data types (type 0x12 used for embedded audio yuv data user defined byte based data reserved rgb data raw data 1 of 4 channel select data type select 8 bits 8 bits word count pixel bytes bits 1 1 8 line start line stop n* n wrd 1 wrd 2 wrd 3 wrd 4 wrd wc- 2 wrd wc -1 wrd wc wrd wc - 3 dout21 dout26 res res no input when bws = low res res p3[7:0] p4[7:0] *pixel count needs to be a multiple of 2 d7 pa-7 d6 pa-6 d5 pa-5 d4 pa-4 d3 pa-3 d2 pa-2 d1 pa-1 d0 pa-0 d7 pb-7 d6 pb-6 d5 pb-5 d4 pb-4 d3 pb-3 d2 pb-2 d1 pb-1 d0 pb-0 downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 40 figure 27. raw 10-bit (double load) output dout 0 dout 1 pa0 pa1 pa2 dout 2 gmsl to csi-2 raw 10 bit (double load, bws = high or open) p4[9:2] packet header p1[9:2] p3[9:2] p2[9:2] p(n-3)[9:2] p(n-2)[9:2] p(n)[9:2] p(n-1)[9:2] packet footer data id word count ecc d6 pb4-0 d7 pb4-1 d4 pa3-0 d5 pa3-1 d2 pb2-0 d3 pb2-1 d0 pa1-0 d1 pa1-1 8 bits 16 bits 8 bits d7 0 d6 0 d5 dt5 d4 dt4 d3 dt3 d2 dt2 d1 dt1 d0 dt0 d7 vc1 d6 vc0 d5 dt5 d4 dt4 d3 dt3 d2 dt2 d1 dt1 d0 dt0 crc ls byte crc ms byte 1 of 4 channel select data type select 8 bits 8 bits line start line stop wrd wc- 2 wrd wc -1 wrd wc wrd wc - 3 hs vs de dout 18/hs dout 19/vs dout 20/de dout 23 dout 26 res res pa-0 pa-1 pa-2 controls fs & fe and packet start/end dout 10 dout 11 dout 12 hs vs de dout 18/hs dout 19/vs dout 20/de dout 0 dout 1 dout 2 pb0 pb1 pb2 dout 9 pa9 pa-9 dout 17 dout 9 pb7 lsb lsb wrd wc - 4 dout 21 pb8 dout 22 pb9 pb-0 pb-1 pb-2 pb-7 dout 10 dout 11 dout 12 dout 17 dout 23 dout 26 res res dout 21 pb-8 dout 22 pb-9 data type 0x00 C 0x07 0x08 C 0x0f 0x10 C 0x17 0x18 C 0x1f 0x30 C 0x37 0x38 C 0x3f 0x20 C 0x27 0x28 C 0x2f description synchronization short packet data types generic short packet data types generic long packet data types (type 0x12 used for embedded audio yuv data user defined byte based data reserved rgb data raw data word count pixel bytes bits 1 1.25 10 n* 1.25n *pixel count needs to be a multiple of 4 d6 pb-8 d7 pb-9 d0 pb-2 d1 pb-3 d2 pb-4 d3 pb-5 d4 pb-6 d5 pb-7 d6 pa-8 d7 pa-9 d0 pa-2 d1 pa-3 d2 pa-4 d3 pa-5 d4 pa-6 d5 pa-7 wrd 1 wrd 2 wrd 3 wrd 4 wrd 5 downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 41 figure 28. raw 12-bit (double load) output dout0 dout1 pa-0 pa-1 pa-2 dout2 gmsl to csi-2 raw 12 bit (double load bws = high or open) p4[11:4] packet header p1[11:4] p3[11:4] p2[11:4] p(n-3)[11:4] p(n-2)[11:4] p(n)[11:4] p(n-1)[11:4] packet footer data id word count ecc 8 bits 16 bits 8 bits d7 0 d6 0 d5 dt5 d4 dt4 d3 dt3 d2 dt2 d1 dt1 d0 dt0 d7 vc1 d6 vc0 d5 dt5 d4 dt4 d3 dt3 d2 dt2 d1 dt1 d0 dt0 crc ls byte crc ms byte data type 0x00 C 0x07 0x08 C 0x0f 0x10 C 0x17 0x18 C 0x1f 0x30 C 0x37 0x38 C 0x3f 0x20 C 0x27 0x28 C 0x2f description synchronization short packet data types generic short packet data types generic long packet data types (type 0x12 used for embedded audio yuv data user defined byte based data reserved rgb data raw data 1 of 4 channel select data type select 8 bits 8 bits word count pixel bytes bits 1 1.5 12 line start line stop n* 1.5n wrd 4 wrd wc- 2 wrd wc -1 wc wc - 3 controls fs & fe and packet start/end dout11 pa-11 wrd 5 lsb wrd wc- 4 *pixel count needs to be a multiple of 2 dout3 pa-3 pa-4 dout4 lsb lsb lsb wrd 6 wrd wc - 4 hs vs de dout18 /hs dout19 /vs dout20 /de dout26 dout12 dout13 dout14 pb-0 pb-1 pb-2 dout17 pb-5 dout21 pb-6 dout15 dout16 pb-3 pb-4 pb-11 d3 pa-7 d2 pa-6 d1 pa-5 d0 pa-4 d7 pa-11 d6 pa-10 d5 pa-9 d4 pa-8 d7 pb-3 d6 pb-2 d3 pa-3 d2 pa-2 d5 pb-1 d4 pb-0 d1 pa-1 d0 pa-0 d3 pb-7 d2 pb-6 d1 pb-5 d0 pb-4 d7 pb-11 d6 pb-10 d5 pb-9 d4 pb-8 wrd 1 wrd 2 wrd 3 downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 42 figure 29. raw 8-bit output dout 0 dout 1 gmsl parallel bit p-0 p-1 p-7 dout 7 dout 8 gmsl to csi-2 raw 8 bit (single load) p4[7:0] packet header p1[7:0] p3[7:0] p2[7:0] p(n-5)[7:0] p(n-3)[7:0] p(n-4)[7:0] p(n-2)[7:0] p(n)[7:0] p(n-1)[7:0] packet footer data id word count ecc 8 bits 16 bits 8 bits d7 0 d6 0 d5 dt5 d4 dt4 d3 dt3 d2 dt2 d1 dt1 d0 dt0 d7 vc1 d6 vc0 d5 dt5 d4 dt4 d3 dt3 d2 dt2 d1 dt1 d0 dt0 crc ls byte crc ms byte data type 0x00 C 0x07 0x08 C 0x0f 0x10 C 0x17 0x18 C 0x1f 0x30 C 0x37 0x38 C 0x3f 0x20 C 0x27 0x28 C 0x2f description synchronization short packet data types generic short packet data types generic long packet data types (type 0x12 used for embedded audio yuv data user defined byte based data reserved rgb data raw data 1 of 4 channel select data type select 8 bits 8 bits word count pixel bytes bits 1 1 8 line start line stop n n wrd 1 wrd 2 wrd 3 wrd 4 wrd wc- 2 wrd wc -1 wrd wc wrd wc - 4 wrd wc - 5 wrd wc - 3 d7 p-7 d6 p-6 d5 p-5 d4 p-4 d3 p-3 d2 p-2 d1 p-1 d0 p-0 hs vs de controls fs & fe and packet start/end dout 18/hs dout 19/vs dout 20/de dout 17 dout 21 dout 26 res res no input when bws = low res res downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 43 figure 30. raw 10-bit output dout0 dout1 p-0 p-1 p-2 dout2 dout10 gmsl to csi-2 raw 10 bit hs vs de dout18 /hs dout19 /vs dout20 /de dout21 dout26 res res dout17 res no input when bws = low dout0 dout1 p-0 p-1 p-2 dout2 dout10 hs vs de dout18 /hs dout19 /vs dout20 /de dout21 dout26 res res dout17 res controls fs & fe and packet start/end dout0 dout1 dout2 dout10 hs vs de dout18 /hs dout19 /vs dout20 /de dout21 dout26 res res dout17 res dout0 dout1 dout2 dout10 p-0 p-1 p-2 hs vs de dout18 /hs dout19 /vs dout20 /de dout21 dout26 res res dout17 res p-0 p-1 p-2 res res res res dout9 p-9 dout9 p-9 dout9 dout9 p-9 p-9 p4[9:2] packet header p1[9:2] p3[9:2] p2[9:2] p(n-3)[9:2] p(n-2)[9:2] p(n)[9:2] p(n-1)[9:2] packet footer data id word count ecc d5 p3-1 d4 p3-0 d3 p2-1 d2 p2-0 d1 p1-1 d0 p1-0 d7 p4-1 d6 p4-0 8 bits 16 bits 8 bits d7 0 d6 0 d5 dt5 d4 dt4 d3 dt3 d2 dt2 d1 dt1 d0 dt0 d7 vc1 d6 vc0 d5 dt5 d4 dt4 d3 dt3 d2 dt2 d1 dt1 d0 dt0 crc ls byte crc ms byte data type 0x00 C 0x07 0x08 C 0x0f 0x10 C 0x17 0x18 C 0x1f 0x30 C 0x37 0x38 C 0x3f 0x20 C 0x27 0x28 C 0x2f description synchronization short packet data types generic short packet data types generic long packet data types (type 0x12 used for embedded audio yuv data user defined byte based data reserved rgb data raw data 1 of 4 channel select data type select 8 bits 8 bits word count pixel bytes bits 1 1.25 10 line start line stop n* 1.25n wrd 1 wrd 2 wrd 3 wrd 4 wrd wc- 2 wrd wc -1 wrd wc wrd wc - 3 wrd 5 lsb lsb wrd wc - 4 d6 p-8 d7 p-9 d0 p-2 d1 p-3 d2 p-4 d3 p-5 d4 p-6 d5 p-7 *pixel count needs to be a multiple of 4 downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 44 figure 31. raw 12-bit output dout 0 dout 1 p-0 p-1 p-2 dout 2 gmsl to csi-2 raw 12 bit p4[11:4] packet header p1[11:4] p3[11:4] p2[11:4] p(n-3)[11:4] p(n-2)[11:4] p(n)[11:4] p(n-1)[11:4] packet footer data id word count ecc 8 bits 16 bits 8 bits d7 0 d6 0 d5 dt5 d4 dt4 d3 dt3 d2 dt2 d1 dt1 d0 dt0 d7 vc1 d6 vc0 d5 dt5 d4 dt4 d3 dt3 d2 dt2 d1 dt1 d0 dt0 crc ls byte crc ms byte data type 0x00 C 0x07 0x08 C 0x0f 0x10 C 0x17 0x18 C 0x1f 0x30 C 0x37 0x38 C 0x3f 0x20 C 0x27 0x28 C 0x2f description synchronization short packet data types generic short packet data types generic long packet data types (type 0x12 used for embedded audio yuv data user defined byte based data reserved rgb data raw data 1 of 4 channel select data type select 8 bits 8 bits word count pixel bytes bits 1 1.5 12 line start line stop n* 1.5n wrd wc- 2 wrd wc -1 wc wc - 3 d3 p-7 d2 p-6 d1 p-5 d0 p-4 d7 p-11 d6 p-10 d5 p-9 d4 p-8 hs vs de dout 18/hs dout 19/vs dout 20/de controls fs & fe and packet start/end dout 11 p-11 wrd 5 lsb wrd wc- 4 *pixel count needs to be a multiple of 2 dout 3 p-3 p-4 dout 4 dout 0 dout 1 p-0 p-1 p-2 dout 2 hs vs de dout 18/hs dout 19/vs dout 20/de dout 11 p-11 dout 3 p-3 p-4 dout 4 lsb lsb lsb wrd 6 wrd wc - 4 dout 21 dout 26 res res no input when bws = low dout 12 dout 17 res res dout 12 dout 17 res res dout 21 dout 26 res res d3 p-7 d2 p-6 d1 p-5 d0 p-4 d7 p-11 d6 p-10 d5 p-9 d4 p-8 d7 p2-3 d6 p2-2 d3 p1-3 d2 p1-2 d5 p2-1 d4 p2-0 d1 p1-1 d0 p1-0 wrd 1 wrd 2 wrd 3 wrd 4 downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 45 figure 32. raw 14-bit output dout0 p-0 dout14 gmsl to csi-2 raw 14 bit hs vs de dout18 /hs dout19 /vs dout20 /de dout21 dout26 res res dout17 res no input when bws = low dout0 p-0 dout14 hs vs de dout18 /hs dout19 /vs dout20 /de dout21 dout26 res res dout17 res controls fs & fe and packet start/end dout0 dout14 hs vs de dout18 /hs dout19 /vs dout20 /de dout21 dout26 res res dout17 res dout0 dout14 p-0 hs vs de dout18 /hs dout19 /vs dout20 /de dout21 dout26 res res dout17 res p-0 res dout5 p-5 dout5 p-5 dout5 dout5 p-5 p-5 p4[13:6] packet header p1[13:6] p3[13:6] p2[13:6] packet footer data id word count ecc p-2 p-3 p-4 p-5 p-0 p-1 8 bits 16 bits 8 bits d7 0 d6 0 d5 dt5 d4 dt4 d3 dt3 d2 dt2 d1 dt1 d0 dt0 d7 vc1 d6 vc0 d5 dt5 d4 dt4 d3 dt3 d2 dt2 d1 dt1 d0 dt0 crc ls byte crc ms byte data type 0x00 C 0x07 0x08 C 0x0f 0x10 C 0x17 0x18 C 0x1f 0x30 C 0x37 0x38 C 0x3f 0x20 C 0x27 0x28 C 0x2f description synchronization short packet data types generic short packet data types generic long packet data types (type 0x12 used for embedded audio yuv data user defined byte based data reserved rgb data raw data 1 of 4 channel select data type select 8 bits 8 bits word count pixel bytes bits 1 1.75 14 line start line stop n* 1.75n wrd 1 wrd 2 wrd 3 wrd 4 wrd 5 word (wc C 6) to (wc C 3) d7 p-13 d0 p-6 d1 p-7 *pixel count needs to be a multiple of 4 msb lsb p4[5:0] p1[5:0] p3[5:0] p2[5:0] p(n-3) to p(n) lsb p(n-3) to p(n) msb word (wc C 2) to wc wrd 6 wrd 7 dout6 p-6 dout6 p-6 dout6 dout6 p-6 p-6 dout13 p-13 dout13 p-13 dout13 dout13 p-13 p-13 res res res downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 46 figure 33. user-defined 24-bit output hs vs de controls fs & fe and packet start/end dout0 dout1 dout18 /hs dout19 /vs dout20 /de dout21 dout22 dout23 dout24 dout25 dout26 gmsl parallel bit ua-0 ua-1 ua-5 dout5 dout6 dout7 dout11 dout12 dout13 dout17 ub-0 ub-1 ub-5 uc-0 uc-1 uc-5 ua-6 ua-7 ub-6 ub-7 uc-6 uc-7 gmsl to csi-2 user-defined 24 bit (bws = high or open) ua2[7:0] packet header uc2[7:0] ub2[7:0] ua1[7:0] uc1[7:0] ub1[7:0] ua(n-1)[7:0] uc(n-1)[7:0] ub(n-1)[7:0] ua(n)[7:0] uc(n)[7:0] ub(n)[7:0] packet footer data id word count ecc 8 bits 16 bits 8 bits d7 0 d6 0 d5 dt5 d4 dt4 d3 dt3 d2 dt2 d1 dt1 d0 dt0 d7 vc1 d6 vc0 d5 dt5 d4 dt4 d3 dt3 d2 dt2 d1 dt1 d0 dt0 crc ls byte crc ms byte data type 0x00 C 0x07 0x08 C 0x0f 0x10 C 0x17 0x18 C 0x1f 0x30 C 0x37 0x38 C 0x3f 0x20 C 0x27 0x28 C 0x2f description synchronization short packet data types generic short packet data types generic long packet data types (type 0x12 used for embedded audio yuv data user defined 24-bit = 0x30 reserved rgb data raw data 1 of 4 channel select data type select 8 bits 8 bits word count pixel bytes bits 1 3 24 line start line stop n 3n wrd 1 wrd 2 wrd 3 wrd 4 wrd wc- 2 wrd wc-1 wrd wc wrd wc-4 wrd 5 wrd 6 wrd wc-5 wrd wc-3 d0 ub-0 d1 ub-1 d2 ub-2 d3 ub-3 d4 ub-4 d5 ub-5 d6 ub-6 d7 ub-7 d0 ua-0 d1 ua-1 d2 ua-2 d3 ua-3 d4 ua-4 d5 ua-5 d6 ua-6 d7 ua-7 d0 uc-0 d1 uc-1 d2 uc-2 d3 uc-3 d4 uc-4 d5 uc-5 d6 uc-6 d7 uc-7 downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 47 figure 34. user-defined 24-bit output dout 0 dout 1 gmsl parallel bit u-0 u-1 u-7 dout 7 dout 8 gmsl to csi-2 user defined 8 bit u4[7:0] packet header u1[7:0] u3[7:0] u2[7:0] u(n-5)[7:0] u(n-3)[7:0] u(n-4)[7:0] u(n-2)[7:0] u(n)[7:0] u(n-1)[7:0] packet footer data id word count ecc 8 bits 16 bits 8 bits d7 0 d6 0 d5 dt5 d4 dt4 d3 dt3 d2 dt2 d1 dt1 d0 dt0 d7 vc1 d6 vc0 d5 dt5 d4 dt4 d3 dt3 d2 dt2 d1 dt1 d0 dt0 crc ls byte crc ms byte data type 0x00 C 0x07 0x08 C 0x0f 0x10 C 0x17 0x18 C 0x1f 0x30 C 0x37 0x38 C 0x3f 0x20 C 0x27 0x28 C 0x2f description synchronization short packet data types generic short packet data types generic long packet data types (type 0x12 used for embedded audio yuv data user defined byte based data (user defined 8-bit = 0x31) reserved rgb data raw data 1 of 4 channel select data type select 8 bits 8 bits word count pixel bytes bits 1 1 8 line start line stop n n wrd 1 wrd 2 wrd 3 wrd 4 wrd wc- 2 wrd wc -1 wrd wc wrd wc - 4 wrd wc - 5 wrd wc - 3 d7 u-7 d6 u-6 d5 u-5 d4 u-4 d3 u-3 d2 u-2 d1 u-1 d0 u-0 hs vs de controls fs & fe and packet start/end dout 18/hs dout 19/vs dout 20/de dout 17 dout 21 dout 26 res res no input when bws = low res res downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 48 auto pixel-per-line feature for proper operation, the device requires the information of number of pixels in de high period. program the pixel count into registers 0x61 and 0x62. alternatively, the device can automatically count the number of pixels in de high period. setting the autoppl bit high enables this function. in this mode, the device counts the number of pixels in every de high period and compares the result with the number of pixels in the previous de high period. if both numbers are within 4 pixels of each other, the deserializer accepts this count as valid count and uses the number to pack- etize the video data. an autoppl error is issued only when the current pixel count does not match the previous pixel count. an invalid count (5 or more pixels) stops the packet transmission and issues an autoppl error. this allows the device to tolerate some noise while alerting the user of an error. table 2 video output map (rgb and yuv) 1. refer to the gmsl serializer data sheet for details. 2. yuv defaults to muxed input mode (cb, y0, cr, y1). set inputbw = 1 to use normal input mode (cby0, cry1). 3. data type available when bws = high or open, only. *vesa/oldi bits are mapped to mipi according to oldi bit (d4 or register 0x60). set oldi bit low when using vesa input or high when using an oldi input. oldi defines bits [5:0] as msb and bits [6:7] as lsb. **12-bit yuv422 sent using csi-2 user-defined data type (0x30). the output byte sequence is cb[11:4], y0[11:4], [cb[3:0], y0[3:0]], cr[11:4], y1[11:4], [cr[3:0], and y1[3:0]]. gmsl input bits 1 rgb yuv422 2 666 565 888 3* 8-bit muxed 10-bit muxed 8-bit 10-bit 3 12-bit 3** din0 r0 r0 r0 y/cb/cr0 y/cb/cr0 cb/cr0 cb/cr0 cb/cr0 din1 r1 r1 r1 y/cb/cr1 y/cb/cr1 cb/cr1 cb/cr1 cb/cr1 din2 r2 r2 r2 y/cb/cr2 y/cb/cr2 cb/cr2 cb/cr2 cb/cr2 din3 r3 r3 r3 y/cb/cr3 y/cb/cr3 cb/cr3 cb/cr3 cb/cr3 din4 r4 r4 r4 y/cb/cr4 y/cb/cr4 cb/cr4 cb/cr4 cb/cr4 din5 r5 g0 r5 y/cb/cr5 y/cb/cr5 cb/cr5 cb/cr5 cb/cr5 din6 g0 g1 g0 y/cb/cr6 y/cb/cr6 cb/cr6 cb/cr6 cb/cr6 din7 g1 g2 g1 y/cb/cr7 y/cb/cr7 cb/cr7 cb/cr7 cb/cr7 din8 g2 g3 g2 y/cb/cr8 y0 cb/cr8 cb/cr8 din9 g3 g4 g3 y/cb/cr9 y1 cb/cr9 cb/cr9 din10 g4 g5 g4 y2 y0 cb/cr10 din11 g5 b0 g5 y3 y1 cb/cr11 din12 b0 b1 b0 y4 y2 y0 din13 b1 b2 b1 y5 y3 y1 din14 b2 b3 b2 y6 y4 y2 din15 b3 b4 b3 y7 y5 y3 din16 b4 b4 y6 y4 din17 b5 b5 y7 y5 din18 hs hs hs hs hs hs hs hs din19 vs vs vs vs vs vs vs vs din20 de de de de de de de de din21 r6 y8 y6 din22 r7 y9 y7 din23 g6 y8 din24 g7 y9 din25 b6 y10 din26 b7 y11 downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 49 clock operation the gmsl deserializer recovers the pixel clock (pclk) from the serial input. this pixel clock is used to time various functions of the device such as the control sig - nals and mclk. the pixel, along with the csi data type, determines the csi hs clock (clk+/-) when the clocks are stable, the lock pin goes high and the clock trans- mitter starts the sot, hs prepare and hs zero sequences and transmits the hs clock in hs differential mode. if the device loses of lock, the clock lane is disabled, and the clock transmitter pulls the line to stop state (lp-11). data-rate selection and csi-2 clock limitations three factors affect the overal useable clock range of the gmsl deserializers: the valid clock range of the gmsl serial input, the mipi csi-2 output, and the data bit width. table 5 lists the valid pclk range at various csi-2 output modes. table 6 shows the valid csi-2 output-channel bit rate. table 3. video output map (raw and user defined) 1. refer to the gmsl serializer data sheet for details. 2. raw datatype defaults to single load. set inputbw = 1 to use double input mode (output sequence pa0, pb0, pa1, pb1). 3. data type available when bws = high or open, only. gmsl input bits 1 raw (double load 2 ) raw (single load 2 ) user defined 8-bit 10-bit 3 12-bit 3 8-bit 10-bit 12-bit 14-bit 24-bit 3 8-bit din0 pa0 pa0 pa0 p0 p0 p0 p0 ua0 u0 din1 pa1 pa1 pa1 p1 p1 p1 p1 ua1 u1 din2 pa2 pa2 pa2 p2 p2 p2 p2 ua2 u2 din3 pa3 pa3 pa3 p3 p3 p3 p3 ua3 u3 din4 pa4 pa4 pa4 p4 p4 p4 p4 ua4 u4 din5 pa5 pa5 pa5 p5 p5 p5 p5 ua5 u5 din6 pa6 pa6 pa6 p6 p6 p6 p6 ub0 u6 din7 pa7 pa7 pa7 p7 p7 p7 p7 ub1 u7 din8 pb0 pa8 pa8 p8 p8 p8 ub2 din9 pb1 pa9 pa9 p9 p9 p9 ub3 din10 pb2 pb0 pa10 p10 p10 ub4 din11 pb3 pb1 pa11 p11 p11 ub5 din12 pb4 pb2 pb0 p12 uc0 din13 pb5 pb3 pb1 p13 uc1 din14 pb6 pb4 pb2 uc2 din15 pb7 pb5 pb3 uc3 din16 pb6 pb4 uc4 din17 pb7 pb5 uc5 din18 hs hs hs hs hs hs hs hs hs din19 vs vs vs vs vs vs vs vs vs din20 de de de de de de de de de din21 pb8 pb6 ua6 din22 pb9 pb7 ua7 din23 pb8 ub6 din24 - pb9 ub7 din25 pb10 uc6 din26 pb11 uc7 downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 50 gmsl clock range the deserializer uses the drs pin/bit and the bws input to set the gmsl pixel clock frequency range ( table 5 ). set drs = 1 for low data rate pixel clock frequency range of 6.25mhz to 16.66mhz. set drs = 0 for high data rate pixel clock frequency range of 12.5mhz to 104mhz. csi-2 clock range the csi-2 ports operate from 80mbps to 1000mbps per channel. the csi-2 output bit rate can be calculated from the pclk rate by the following equation: csi rate = pclk x width/lanes where: pclk = input pclk rate lanes = number of csi-2 lanes used width = bit width of the input data (see table 5 or table 6 ) high-bandwidth mode the deserializer uses a 27-bit high-bandwidth mode to support 24-bit rgb at 104mhz pixel clock. set bws = open in both the serializer and deserializer to use high- bandwidth mode. in high-bandwidth mode, the deserial- izer decodes hs, vs, de, and cntl[3:0] from special packets. packets are sent by replacing a pixel before the rising edge and after the falling edge of the hs, vs, and de signals. however, for cntl[3:0], which is not always continuously sampled, packets always replace a pixel before the transition of the sampled cntl[3:0]. keep hs, vs, and de low pulse widths at least two pixel clock cycles. by default, cntl[3:0] are sampled continuously when de is low. cntl[3:0] are sampled only on hs/vs transitions when de is high. if de triggering of encoded packets is not desired, set the serializers disdetrig = 0 and the cntltrig bits to their desired value (reg- ister 0x15) to change the cntl triggering behavior. set detren = 0 on the deserializer when de is not periodic. audio channel the audio channel supports 8khz to 192khz audio sampling rates and audio word lengths from 8 bits to 32 bits (2-channel i 2 s), or 64 to 256 bits (tdm64 to tdm256). the audio bit clock (sck) does not have to be synchronized with pixel clock. the serializer automatically encodes audio data into a single-bit stream synchronous with pixel clock. the deserializer decodes the audio stream and stores audio words in a fifo. audio rate detection uses an internal oscillator to continuously determine the audio data rate and output the audio in i 2 s format. the audio channel is enabled by default. when the audio channel is disabled, the sd/him is treated as an auxiliary control signal. since the encoded audio data sent through the serial link is synchronized with pixel clock (through acb), low pixel clock frequencies limit the maximum audio sampling rate. table 5 lists the maximum audio sampling rate for various pixel clock frequencies. spread spectrum from the serializer do not affect the i 2 s/tdm data rate or ws clock frequency. audio channel input the audio channel input works with 8-channel tdm and stereo i 2 s, as well as nonstandard formats. the input format is shown in figure 35 . the period of the ws can be 8 to 256 sck periods. the ws frame starts with the falling edge and can be low for 1 to 255 sck periods. sd is one sck period, sampled on the rising edge. msb/lsb order, zero padding, or any other significance assigned to the serial data does not affect operation of the audio channel. the polarity for ws and sck edges is programmable. figure 36 , figure 37 , figure 38 , and figure 39 are examples of acceptable input formats. figure 35. audio channel input format frame 16 to 256 bits 0 1 2 sck sd ws n downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 51 table 5. gmsl data-rate selection table table 4. control output map note: see the high-bandwidth mode section for details on timing requirements. *outputs used only when the respective color lookup tables are enabled. **not encrypted when hdcp is enabled (max9290 only). table 6. input pixel clock range (mhz) control outputs mode 24-bit mode (bws = low) high-bandwidth mode (bws = mid) 32-bit mode (bws = high) cntl0 not used used* not used cntl1 not used used* used** cntl2 not used used* used** cntl3 not used used* not used drs bit setting bws pin setting pixel clock range (mhz) 0 (high data rate) low (24-bit mode) 16.66 to 104 mid (high-bandwidth mode) 36.66 to 104 high (32-bit mode) 12.5 to 78 1 (low data rate) low 8.33 to 16.66 mid 18.33 to 36.66 high 6.25 to 12.5 gmsl bit width csi-2 output modes number of csi-2 lanes drs low drs high bws low bws open bws high bws low bws open bws high 8 raw8 (single load) yuv422 8b muxed 1 16.67 to 104 36.67 to 104 12.5 to 78 10 to 16.67 18.33 to 36.67 10 to 12.5 2 20 to 104 36.67 to 104 20 to 78 do not use 20 to 36.67 do not use 3 30 to 104 36.67 to 104 30 to 78 do not use 30 to 36.67 do not use 4 40 to 104 40 to 104 40 to 78 do not use do not use do not use downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 52 table 6. input pixel clock range (mhz) (continued) gmsl bit width csi-2 output modes number of csi-2 lanes drs low drs high bws low bws open bws high bws low bws open bws high 10 raw10 (single load) yuv422 10b muxed 1 16.67 to 100 36.67 to 100 12.5 to 78 8.333 to 16.67 18.33 to 36.67 8 to 12.5 2 16.67 to 104 36.67 to 104 16 to 78 16 to 16.67 18.33 to 36.67 do not use 3 24 to 104 36.67 to 104 24 to 78 do not use 24 to 36.67 do not use 4 32 to 104 36.67 to 104 32 to 78 do not use 32 to 36.67 do not use 12 raw12 (single load) 1 16.67 to 83.33 36.67 to 83.3 12.5 to 78 8.333 to 16.67 18.33 to 36.67 6.667 to 12.5 2 16.67 to 104 36.67 to 104 13.33 to 78 13.33 to 16.67 18.33 to 36.67 do not use 3 20 to 104 36.67 to 104 20 to 78 do not use 20 to 36.67 do not use 4 26.67 to 104 36.67 to 104 26.67 to 78 do not use 26.67 to 36.67 do not use 14 raw14 (single load) 1 16.67 to 71.43 36.67 to 71.43 12.5 to 71.43 8.333 to 16.67 18.33 to 36.67 6.25 to 12.5 2 16.67 to 104 36.67 to 104 12.5 to 78 11.43 to 16.67 18.33 to 36.67 11.43 to 12.5 3 17.14 to 104 36.67 to 104 17.14 to 78 do not use 18.33 to 36.67 do not use 4 22.86 to 104 36.67 to 104 22.86 to 78 do not use 22.86 to 36.67 do not use 16 raw8 (double load) yuv442 8b rgb565 1 16.67 to 62.5 36.67 to 62.5 12.5 to 62.5 8.333 to 16.67 18.33 to 36.67 6.25 to 12.5 2 16.67 to 104 36.67 to 104 12.5 to 78 10 to 16.67 18.33 to 36.67 10 to 12.5 3 16.67 to 104 36.67 to 104 15 to 78 15 to 16.67 18.33 to 36.67 do not use 4 20 to 104 36.67 to 104 20 to 78 do not use 20 to 36.67 do not use downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 53 table 6. input pixel clock range (mhz) (continued) gmsl bit width csi-2 output modes number of csi-2 lanes drs low drs high bws low bws open bws high bws low bws open bws high 18 rgb666 1 16.67 to 55.56 36.67 to 55.56 12.5 to 55.56 8.333 to 16.67 18.33 to 36.67 6.25 to 12.5 2 16.67 to 104 36.67 to 104 12.5 to 78 8.889 to 16.67 18.33 to 36.67 8.889 to 12.5 3 16.67 to 104 36.67 to 104 13.33 to 78 13.33 to 16.67 18.33 to 36.67 do not use 4 16.67 to 104 36.67 to 104 17.78 to 78 do not use 18.33 to 36.67 do not use 20 raw10 (double load) yuv442 10b 1 do not use 36.67 to 50 12.5 to 50 do not use 18.33 to 36.67 6.25 to 12.5 2 do not use 36.67 to 100 12.5 to 78 do not use 18.33 to 36.67 8 to 12.5 3 do not use 36.67 to 104 12.5 to 78 do not use 18.33 to 36.67 12 to 12.5 4 do not use 36.67 to 104 16 to 78 do not use 18.33 to 36.67 do not use 24 raw12 (double load) yub442 12b rgb888 user-deined 8b user-deined 24b 1 do not use 36.67 to 41.67 12.5 to 41.67 do not use 18.33 to 36.67 6.25 to 12.5 2 do not use 36.67 to 83.33 12.5 to 78 do not use 18.33 to 36.67 6.667 to 12.5 3 do not use 36.67 to 104 12.5 to 78 do not use 18.33 to 36.67 10 to 12.5 4 do not use 36.67 to 104 13,33 to 78 do not use 18.33 to 36.67 do not use downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 54 table 7. output csi-2 data rate range (mbps) gmsl bit width csi-2 output modes number of csi-2 lanes drs low drs high bws low bws open bws high bws low bws open bws high 8 raw8 (single load) yuv422 8b muxed 1 133.3 to 832 293.3 to 832 100 to 624 80 to 133.3 146.7 to 293.3 80 to 100 2 80 to 416 146.7 to 832 80 to 312 do not use 80 to 146.7 do not use 3 80 to 277.3 97.78 to 277.3 80 to 208 do not use 80 to 97.76 do not use 4 80 to 208 80 to 208 80 to 156 do not use do not use do not use 10 raw10 (single load) yuv422 10b muxed 1 166.7 to 1000 366.7 to 1000 125 to 780 83.33 to 166.7 183.3 to 366.7 80 to 125 2 83.33 to 520 183.3 to 520 80 to 390 80 to 83.33 91.67 to 183.3 do not use 3 80 to 346.7 122.22 to 346.7 80 to 260 do not use 80 to 122.2 do not use 4 80 to 260 91.67 to 260 80 to 195 do not use 80 to 91.67 do not use 12 raw12 (single load) 1 200 to 1000 440 to 1000 150 to 936 100 to 200 220 to 440 80 to 150 2 100 to 624 220 to 624 80 to 468 80 to 100 110 to 220 do not use 3 80 to 416 147 to 416 80 to 312 do not use 80 to 147 do not use 4 80 to 312 147 to 312 80 to 234 do not use 80 to 110 do not use 14 raw14 (single load) 1 233.3 to 1000 513.3 to 1000 175 to 1000 116.7 to 233.3 256.7 to 513.3 87.5 to 175 2 116.7 to 728 256.7 to 1728 87.5 to 546 80 to 116.7 128.3 to 256.7 80 to 87.5 3 80 to 485.3 171.1 to 485.3 80 to 364 do not use 80 to 171.1 do not use 4 80 to 364 80 to 364 80 to 273 do not use 80 to 128.3 do not use downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 55 table 7. output csi-2 data rate range (mbps) (continued) gmsl bit width csi-2 output modes number of csi-2 lanes drs low drs high bws low bws open bws high bws low bws open bws high 16 raw8 (double load) yuv442 8b rgb565 1 256.7 to 1000 586.7 to 1000 200 to 1000 133.3 to 266.7 293.3 to 586.7 100 to 200 2 133.3 to 832 293.3 to 832 100 to 624 80 to 133.3 146.7 to 293.3 80 to 100 3 88.89 to 554.7 195.6 to 554.7 80 to 416 80 to 88.89 97.78 to 195.6 do not use 4 80 to 416 146.7 to 832 80 to 312 do not use 80 to 146.7 do not use 18 rgb666 1 300 to 1000 660 to 1000 225 to 1000 150 to 300 330 to 660 112.5 to 225 2 150 to 936 330 to 936 112.5 to 702 80 to 150 165 to 330 80 to 112.5 3 100 to 624 110 to 624 80 to 468 80 to 100 110 to 220 do not use 4 80 to 468 165 to 468 80 to 351 do not use 82.5 to 165 do not use 20 raw10 (double load) yuv442 10b 1 do not use 733.3 to 1000 250 to 1000 do not use 366.6 to 733.3 120 to 250 2 do not use 366.7 to 1000 125 to 780 do not use 183.3 to 366.7 80 to 125 3 do not use 244.4 to 93.3 83.33 to 520 do not use 122.2 to 244.4 80 to 83.33 4 do not use 183.3 to 520 80 to 390 do not use 91.67 to 183.3 do not use 24 raw12 (double load) yub442 12b rgb888 user deined 8b user deined 24b 1 do not use 880 to 1000 300 to 1000 do not use 440 to 880 150 to 300 2 do not use 440 to 1000 150 to 936 do not use 220 to 440 80 to 150 3 do not use 293.3 to 832 100 to 624 do not use 146.7 to 293.3 80 to 100 4 do not use 220 to 624 80 to 468 do not use 110 to 220 do not use downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 56 table 8. maximum audio ws frequency (khz) for various pixel clock frequencies +max ws rate is greater than 192khz. *drs = 0 pixel clock frequency is equal to 2x the drs = 1 pixel clock frequency. channels bits per channel pixel clock frequency (drs = 0*) (mhz) 12.5 15.0 16.6 20.0 25.0 30.0 35.0 40.0 45.0 50.0 100 2 8 + + + + + + + + + + + 16 + + + + + + + + + + + 18 185.5 + + + + + + + + + + 20 174.6 + + + + + + + + + + 24 152.2 182.7 + + + + + + + + + 32 123.7 148.4 164.3 + + + + + + + + 4 8 + + + + + + + + + + + 16 123.7 148.4 164.3 + + + + + + + + 18 112.0 134.4 148.8 179.2 + + + + + + + 20 104.2 125.0 138.3 166.7 + + + + + + + 24 88.6 106.3 117.7 141.8 177.2 + + + + + + 32 69.9 83.8 92.8 111.8 139.7 167.6 + + + + + 6 8 152.2 182.7 + + + + + + + + + 16 88.6 106.3 117.7 141.8 177.2 + + + + + + 18 80.2 93.3 106.6 128.4 160.5 + + + + + + 20 73.3 88.0 97.3 117.3 146.6 175.9 + + + + + 24 62.5 75.0 83.0 100 125 150 175 + + + + 32 48.3 57.9 64.1 77.2 96.5 115.9 135.2 154.5 173.8 + + 8 8 123.7 148.4 164.3 + + + + + + + + 16 69.9 83.8 92.8 111.8 139.7 167.6 + + + + + 18 62.5 75.0 83.0 100.0 125.0 150.0 175.0 + + + + 20 57.1 68.5 75.8 91.3 114.2 137.0 159.9 182.7 + + + 24 48.3 57.9 64.1 77.2 96.5 115.9 135.2 154.5 173.8 + + 32 37.1 44.5 49.3 59.4 74.2 89.1 103.9 118.8 133.6 148.4 + color coding < 48khz48khz to 96khz 96khz to 192khz > 192khz downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 57 figure 36. 8-channel tdm (24-bit samples, padded with zeros) figure 37. 6-channel tdm (24-bit samples, no padding) figure 38. stereo i 2 s (24-bit samples, padded with zeros) ws sck sd ch1 32 sck ch2 ch3 ch4 ch5 256 sck ch6 ch7 ch8 msb 24-bit data lsb 8 bits zero ws sck sd ch1 ch2 ch3 ch4 ch5 ch6 24 sck 24-bit data 144 sck ws sck sd ch1 ch2 ch3 ch4 ch5 ch6 24 sck 24-bit data 144 sck downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 58 audio channel output ws, sck, and sd are output with the same timing relationship they had at the audio input, except that ws is always 50% duty cycle (regardless of the duty cycle of ws at the input). the output format is shown in figure 40 . ws and sck can be driven by the audio source (clock master) or the audio sink (clock slave). buffer underflow and overflow flags are available to the sink as clock slave through i 2 c for clock frequency adjustment. data are sampled on the rising edge. ws and sck polarity is programmable. additional mclk output for audio applications some audio dacs, such as the max9850, do not require a synchronous main clock (mclk), while other dacs require a separate mclk for operation. for audio applica - tions that cannot use ws directly, the deserializer provides a divided mclk output at either cntl2 or cntl0 (deter - mined by mclkpin bit setting) at the expense of one less control line. by default, mclk is turned off. set mclkdiv (deserializer register 0x12, d[6:0]) to a nonzero value to enable the mclk output. set mclkdiv to 0x00 to disable mclk and set cntl2 or cntl0 as a control output. the output mclk frequency is: src mclk f f mclkdiv = where:f src is the mclk source frequency (see table 9 ) mclkdiv is the divider ratio from 1 to 127 choose mclkdiv values so that f mclk is not greater than 60mhz. mclk frequencies derived from pixel clock (mclksrc = 0) are not affected by spread-spectrum settings in the deserializer. enabling spread spectrum in the serializer, however, introduces spread spectrum into mclk. spread-spectrum settings of either device do not affect mclk frequencies derived from the internal oscillator. the internal oscillator frequency ranges from 100mhz to 150mhz over all process corners and operating conditions. alternatively, set mclkws = 1 (0x15 d1) to output ws from mclk. audio output timing sources the deserializer has multiple options for audio data output timing. by default, the deserializer provides the output timing based on the incoming data rate (through a fifo) and an internal oscillator. to use a system-sourced clock, set the audiomode bit to 1 (d5 of register 0x02) to set ws and sck as inputs on the deserializer side. the deserializer uses a fifo to smooth out the differences in input and output audio timing. registers 0x78 and 0x79 store the fifo overflow/ underflow information for use with external ws/sck timing. the fifo drops data packets during fifo over- flow. by default, the fifo repeats the last audio packet during fifo underflow when no audio data is available. set the audufbeh bit (d2 of register 0x01d) to 1 to output all zeroes during underflow. reverse control channel the serializer uses the reverse control channel to receive i 2 c/uart and gpo signals from the deserializer in the opposite direction of the video stream. the reverse control channel and forward video data coexist on the same serial cable forming a bidirectional link. the reverse control channel operates independently from the forward control channel. the reverse control channel is available 2ms after power-up. the serializer temporarily disables the reverse control channel for 500s after starting/ stopping the forward serial link. figure 39. stereo i 2 s (16-bit samples, no padding) 32 sck left channel right channel 16 sck 16-bit data ws sck sd downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 59 control channel and register programming the control channel is available for the c to send and receive control data over the serial link simultaneously with the high-speed data. the c controls the link from either the serializer or the deserializer side to support video-display or image-sensing applications. the control channel between the c and serializer or deserializer runs in base mode or bypass mode according to the mode-selection input (ms) of the device connected to the c. base mode is a half-duplex control channel and bypass mode is a full-duplex control channel. the total maximum forward or reverse control-channel delay is 2s (uart) or 2-bit times (i 2 c) from the input of one device to the output of the other. i 2 c delay is measured from a start condition to a stop condition. uart interface in base mode, the c is the host and can access the registers of both the serializer and deserializer from either side of the link using the gmsl uart protocol. the c can also program the peripherals on the remote side by sending the uart packets to the serializer or deserializer, with the uart packets converted to i 2 c by the device on the remote side of the link. the c communicates with a uart peripheral in base mode (through inttype register settings), using the half-duplex default gmsl uart protocol of the serializer/deserializer. the device addresses of the serializer and deserializer in base mode are programmable. when the peripheral interface is i 2 c, the serializer/ deserializer convert uart packets to i 2 c that have device addresses different from those of the serializer or deserializer. the converted i 2 c bit rate is the same as the original uart bit rate. the deserializer uses differential line coding to send signals over the reverse channel to the serializer. the bit rate of the control channel is 9.6kbps to 1mbps in both directions. the serializer and deserializer automatically detect the control- channel bit rate in base mode. packet bit-rate changes can be made in steps of up to 3.5 times higher or lower than the previous bit rate. see the changing the clock frequency section for more information. table 9. f src settings *mclk is not divided when using ws as the mclk source. mclk divider must still be set to a nonzero number for mclk to be enabled. figure 40. audio channel output format mclkws setting (register 0x15, d1) mclksrc setting (register 0x12, d7) data rate setting bit-width setting mclk source frequency (f src ) 0 0 high speed (drs = 0) 24-bit or high-bandwidth mode 3 x f pixel 32-bit mode 4 x f pixel low speed (drs = 1) 24-bit or high-bandwidth mode 6 x f pixel 32-bit mode 8 x f pixel 1 internal oscillator (120mhz typ) 1 ws* i 2 s tdm 256 sck sd/him ws sck sd/him ws 8 to 32 bits 256 bits downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 60 figure 41 shows the uart protocol for writing and reading in base mode between the c and the serializer/deserializer. figure 42 shows the uart data format. even parity is used. figure 43 and figure 44 detail the formats of the sync byte (0x79) and the ack byte (0xc3). the c and the connected slave chip generate the sync byte and ack byte, respectively. events such as device wake-up and gpi generate transitions on the control channel that can be ignored by the c. data written to the deserial- izer registers do not take effect until after the ack byte is sent. this allows the c to verify that write commands are received without error, even if the result of the write command directly affects the serial link. the slave uses the sync byte to synchronize with the host uarts data rate. if the gpi or ms inputs of the deserializer toggle while there is control-channel communication, or if a line fault occurs, the control-channel communication is cor- rupted. in the event of a missed or delayed acknowledge (~1ms due to control channel timeout), the c should assume there was an error in the packet transmission or response. in base mode, the c must keep the uart tx/ rx lines high no more than four bit times between bytes in a packet. keep the uart tx/rx lines high for at least 16 bit times before starting to send a new packet. figure 41. gmsl uart protocol for base mode figure 42. gmsl uart data format for base mode figure 43. sync byte (0x79) figure 44. ack byte (0xc3) write data format sync dev addr + r/w reg addr number of bytes sync dev addr + r/w reg addr number of bytes byte 1 byte n ack byte n byte 1 ack master reads from slave read data format master writes to slave master writes to slave master reads from slave start d0 d1 d2 d3 d4 d5 d6 d7 parity stop 1 uart frame frame 1 frame 2 frame 3 stop start stop start start d0 1 0 0 1 1 1 1 0 d1 d2 d3 d4 d5 d6 d7 parity stop start d0 1 1 0 0 0 0 1 1 d1 d2 d3 d4 d5 d6 d7 parity stop downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 61 as shown in figure 45 , the remote-side device converts packets going to or coming from the peripherals from uart format to i 2 c format and vice versa. the remote device removes the byte number count and adds or receives the ack between the data bytes of i 2 c. the i 2 c bit rate is the same as the uart bit rate. interfacing command-byte-only i 2 c devices with uart the deserializers uart-to-i 2 c conversion can interface with devices that do not require register addresses, such as the max7324 gpio expander. in this mode, the i 2 c master ignores the register address byte and directly reads/ writes the subsequent data bytes ( figure 46 ). change the communication method of the i 2 c master using the i2cmethod bit. i2cmethod = 1 sets command-byte- only mode, while i2cmethod = 0 sets normal mode where the first byte in the data stream is the register address. uart bypass mode in bypass mode, the deserializers ignore uart com- mands from the c and the c communicates with the peripherals directly using its own defined uart proto- col. the c cannot access the serializer/deserializers registers in this mode. peripherals accessed through the forward control channel using the uart interface need to handle at least one pixel clock period 10ns of jitter due to the asynchronous sampling of the uart signal by pixel clock. set ms = high to put the control channel into bypass mode. for applications with the c connected to the deserializer, there is a 1ms wait time between setting ms high and the bypass control channel being active. there is no delay time when switching to bypass mode when the c is connected to the serial- izer. do not send a logic-low value longer than 100s to ensure proper gpo functionality. bypass mode accepts bit rates down to 10kbps in either direction. see the gpo/gpi control section for gpi functionality limitations. the control-channel data pattern should not be held low longer than 100s if gpi control is used. figure 45. format conversion between gmsl uart and i 2 c with register address (i2cmethod = 0) 11 sync frame register address number of bytes device id + wr data 0 dev id a 11 11 11 11 data n 11 11 s 1 1 1 ack frame 7 : master to slave 8 serializer/deserializer peripheral w 1 reg addr 8 a 1 1 8 1 11 sync frame register address number of bytes device id + rd 11 11 11 11 ack frame data 0 11 data n 11 uart-to-i 2 c conversion of write packet (i2cmethod = 0) uart-to-i 2 c conversion of read packet (i2cmethod = 0) s: start p: stop a: acknowledge : slave to master data 0 a data n a p dev id a s 1 1 7 w 1 dev id a s 1 1 7 r 1 data n p 1 8 a 1 data 0 8 a 1 reg addr 8 a 1 c serializer/deserializer c serializer/deserializer serializer/deserializer peripheral downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 62 i 2 c interface in i 2 c-to-i 2 c mode, the deserializers control-channel interface sends and receives data through an i 2 c- compatible 2-wire interface. the interface uses a serial- data line (sda) and a serial-clock line (scl) to achieve bidirectional communication between master and slave(s). a c master initiates all data transfers to and from the device and generates the scl clock that synchronizes the data transfer. when an i 2 c transaction starts on the local-side devices control-channel port, the remote-side devices control-channel port becomes an i 2 c master that interfaces with remote-side i 2 c peripherals. the i 2 c master must accept clock stretching that is imposed by the deserializer (holding scl low). the sda and scl lines operate as both an input and an open-drain output. pullup resistors are required on sda and scl. each transmission consists of a start condition ( figure 6 ) sent by a master, followed by the devices 7-bit slave address plus a r/w bit, a register address byte, one or more data bytes, and finally a stop condition. figure 46. format conversion between gmsl uart and i 2 c with register address (i2cmethod = 1) : master to slave serializer/deserializer serializer/deserializer serializer/deserializer uart-to-i 2 c conversion of read packet (i2cmethod = 1) uart-to-i 2 c conversion of write packet (i2cmethod = 1) c serializer/deserializer c sync frame 11 11 11 11 11 11 11 11 11 11 11 11 11 11 device id + rd register address number of bytes sync frame device id + wr register address number of bytes data 0 data n ack frame ack frame data 0 data n data n a data 0 w a dev id s a p peripheral peripheral s 1 1 1 8 8 8 1 11 1 7 1 1 8 1 1 1 7 dev id r a a a p data 0 data n : slave to master s: start p: stop a: acknowledge downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 63 start and stop conditions both scl and sda remain high when the interface is not busy. a master signals the beginning of a transmission with a start (s) condition by transitioning sda from high to low while scl is high (see figure 47 ). when the mas- ter has finished communicating with the slave, it issues a stop (p) condition by transitioning sda from low to high while scl is high. the bus is then free for another transmission. bit transfer one data bit is transferred during each clock pulse ( figure 48 ). the data on sda must remain stable while scl is high. acknowledge the acknowledge bit is a clocked 9th bit that the recipient uses to handshake receipt of each byte of data ( figure 49 ). thus, each byte transferred effectively requires 9 bits. the master generates the 9th clock pulse, and the recipi- ent pulls down sda during the acknowledge clock pulse. the sda line is stable low during the high period of the clock pulse. when the master is transmitting to the slave device, the slave device generates the acknowledge bit because the slave device is the recipient. when the slave device is transmitting to the master, the master generates the acknowledge bit because the master is the recipient. the device generates an acknowledge even when the forward control channel is not active. to prevent acknowl- edge generation when the forward control channel is not active, set the i2clocack bit low. figure 47. start and stop conditions figure 48. bit transfer sda scl start condition stop condition s p sda scl data line stable; data valid change of data allowed downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 64 slave address the deserializers have 7-bit long slave addresses. the bit following a 7-bit slave address is the r/w bit, which is low for a write command and high for a read command. the slave address for the deserializer is xx01xxx1 for read commands and xx01xxx0 for write commands. see figure 50 . figure 49. acknowledge figure 50. slave address scl sda by transmitter clock pulse for acknowledge start condition sda by receiver 1 2 8 9 s sda x ack scl msb lsb x x r/w 0 1 x x downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 65 bus reset the device resets the bus with the i 2 c start condition for reads. when the r/w bit is set to 1, the deserializers transmit data to the master, thus the master is reading from the device. format for writing writes to the deserializers comprise the transmission of the slave address with the r/w bit set to zero, followed by at least 1 byte of information. the first byte of informa- tion is the register address or command byte. the register address determines which register of the device is to be written by the next byte, if received. if a stop (p) condi- tion is detected after the register address is received, the device takes no further action beyond storing the register address ( figure 51 ). any bytes received after the register address are data bytes. the first data byte goes into the register selected by the register address, and subsequent data bytes go into subsequent registers ( figure 52 ). if multiple data bytes are transmitted before a stop con- dition, these bytes are stored in subsequent registers because the register addresses autoincrement. figure 51. format for i 2 c write figure 52. format for write to multiple registers s 1 0 0 0 address = 0x80 0 = write 0 0 0 0 a 0 0 0 0 register address = 0x00 0 0 0 0 a p d7 d6 d5 d4 register 0x00 write data d3 d2 d1 d0 a s = start bit p = stop bit a = ack d_ = data bit s = start bit p = stop bit a = ack n = nack d_ = data bit s 1 0 0 0 address = 0x80 0 = write 0 0 0 0 a 0 0 0 0 register address = 0x00 0 0 0 0 a d7 d6 d5 d4 register 0x00 write data d3 d2 d1 d0 a d7 p d6 d5 d4 register 0x01 write data d3 d2 d1 d0 n downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 66 format for reading the deserializers are read using the internally stored register address as an address pointer, the same way the stored register address is used as an address pointer for a write. the pointer autoincrements after each data byte is read using the same rules as for a write. thus, a read is initiated by first configuring the register address by performing a write ( figure 53 ). the master can now read consecutive bytes from the device, with the first data byte being read from the register address pointed by the previ- ously written register address. once the master sends a nack, the device stops sending valid data. i 2 c communication with remote-side devices the deserializers support i 2 c communication with a peripheral on the remote side of the communication link using scl clock stretching. while multiple masters can reside on either side of the communication link, arbitration is not provided. the connected masters need to support scl clock stretching. the remote-side i 2 c bit rate range must be set according to the local-side i 2 c bit rate. supported remote-side bit rates can be found in table 10 . set the i2cmstbt (register 0x1c) to set the remote i 2 c bit rate. if using a bit rate different from 400kbps, local- and remote-side i 2 c setup and hold times should be adjusted by setting the i2cslvsh register settings on both sides. figure 53. format for i 2 c read table 10. i 2 c bit-rate ranges local bit rate remote bit rate range i2cmstbt setting f > 50kbps up to 1mbps any 20kbps > f > 50kbps up to 400kbps up to 110 f < 20kbps up to 10kbps 000 s = start bit p = stop bit a = ack n = nack d_ = data bit s s 1 0 0 0 address = 0x80 0 = write 0 0 0 0 a 1 = read repeated start 0 0 0 0 register address = 0x00 0 0 0 0 a 1 0 0 0 address = 0x81 0 0 0 1 a d7 p d6 d5 d4 register 0x00 read data d3 d2 d1 d0 n downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 67 i 2 c address translation the deserializers support i 2 c address translation for up to two device addresses. use address translation to assign unique device addresses to peripherals with limited i 2 c addresses. source addresses (address to translate from) are stored in registers 0x18 and 0x1a. destination addresses (address to translate to) are stored in registers 0x19 and 0x1b. in a multilink situation where there are multiple deserial- izers and/or peripheral devices connected to these serial- izers, the deserializers support broadcast commands to control these multiple devices. select an unused device address to use as a broadcast device address. program all the remote-side serializer devices to translate the broadcast device address (source address stored in reg - isters 0x0f, 0x11) to the peripherals address (destination address stored in registers 0x10, 0x12). any commands sent to the broadcast address (selected unused address) are sent to all deserializers and/or peripheral devices con- nected to the deserializers whose addresses match the translated broadcast address. gpo/gpi control gpo on the serializer follows gpi transitions on the dese- rializer. this gpo/gpi function can be used to transmit signals such as a frame sync in a surround-view camera system. the gpi-to-gpo delay is 0.35ms max. keep time between gpi transitions to a minimum 0.35ms. this includes transitions from the other deserializer in coax splitter mode. bit d4 of register 0x06 in the deserializer stores the gpi input state. gpo is low after power-up. the c can set gpo by writing to the setgpo register bit. do not send a logic-low value on the deserializer rx/ sda input (uart mode) longer than 100s in either base or bypass mode to ensure proper gpo/gpi functionality. line equalizer the deserializer includes an adjustable line equalizer to further compensate cable attenuation at high frequencies. the cable equalizer has 11 selectable levels of compen- sation from 2.1db to 13db ( table 11 ). to select other equalization levels, set the corresponding register bits in the deserializer (0x05 d[3:0]). use equalization in the deserializer, together with preemphasis in the serializer, to create the most reliable link for a given cable. hs/vs/de tracking the deserializer has tracking to filter out hs/vs/de bit or packet errors. hs/vs/de tracking is on by default when the device is in high-bandwidth mode (bws = open), and off by default when in 24-bit or 32-bit mode (bws = low or high). set/clear hvtren (d6 of register 0x15) to enable/disable hs/vs tracking. set/clear detren (d5 of register 0x15) to enable/disable de tracking. by default, the device uses a partial and full periodic tracking of hs/de. set hvtrmode = 0 (d4 of register 0x15) to disable full periodic tracking. hs/vs/de tracking can be turned on in 24-bit and 32-bit modes to track and correct against bit errors in hs/vs/de link bits. serial input the device can receive serial data from two kinds of cable: 100 twisted pair and 50 coax. (contact the factory for devices compatible with 75 cables). table 11. cable equalizer boost levels boost setting (0x05 d[3:0]) typical boost gain (db) 0000 2.1 0001 2.8 0010 3.4 0011 4.2 0100 5.2 power-up default when eqs is set high 0101 6.2 0110 7 0111 8.2 1000 9.4 1001 10.7 power-up default when eqs is set low 1010 11.7 1011 13 downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 68 coax splitter mode in coax mode, out+ and out- of the serializer are active. this enables the use as a 1:2 splitter ( figure 54 ). in coax mode, connect out+ to in+ of the deserializer. connect out- to in- of the second deserializer. control-channel data is broadcast from the serializer to both deserializers and their attached peripherals. assign a unique address to send control data to one deserializer. leave all unused in_ pins unconnected, or connect them to ground through 50 and a capacitor for increased power-supply rejection. if out- is not used, connect out- to avdd through a 50 resistor ( figure 55 ). when there are cs at the serializer, and at each deserializer, only one c can communicate at a time. disable forward and reverse channel links according to the communicating deserializer connection to prevent contention in i 2 c-to-i 2 c mode. use enrevp or enrevn register bits to disable/enable the control channel link. in uart mode, the serializer provides arbitration of the control-channel link. figure 54. 2:1 coax splitter connection diagram figure 55. coax connection diagram out+ out- optional components for increased power-supply rejection in+in- in+in- max9288max9290 max9288 max9290 gmsl serializer out+ out- in+ optional components for increased power-supply rejection in- avdd 50 ? max9288max9290 gmsl serializer downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 69 cable type coniguration input cx/tp determine the power-up state of the serial input. in coax mode, cx/tp also determine which coax input is active, along with the default device address ( table 12 ). color lookup tables the deserializer includes three color lookup tables (lut) to support automatic translation of pixel values. the lut can be used for rgb666, rgb888, and user-defined generic 8-bit csi-2 outputs. this feature can be used for color gamma correction, brightness/contrast or for other purposes. there are three lookup tables, each 8 bits wide and 256 entries deep, enabling a 1-to-1 translation of 8-bit input values to any 8-bit output value for each color (24 bits total). programming and verifying lut data the c must set the lutprog register bit to 1 before programming and verifying the tables. to program a lut, the c generates a write packet with register address set to the assigned register address for respective lut (0x7d, 0x7e, or 0x7f). the deserializer writes data in the packet to the respective lut starting from the lut address location set in the lutaddr register. successive bytes in the data packet are written to the next lut address location; however, each new data-packet write starts from the address location stored in the lutaddr register. use 0x00 for lutaddr and 0x00 as the number of bytes field in uart packet, when writing a 256-byte data block, because 8-bit-wide number of bytes field cannot normally represent 9-bit wide 256 value. there is no number of bytes field in i 2 c-to-i 2 c modes. to read back the contents of an lut, the c generates a read packet with register address set to the assigned register address for respective lut (0x7d, 0x7e, or 0x7f). the deserializer outputs read data from the respective lut starting from the lut address location set in the lut_addr register. similar to the write operation, use 0x00 for lutaddr and 0x00 as the number of bytes field in uart packet, when reading a 256-byte data block. lut color translation after power-up or going out of sleep or power-down modes, lut translation is disabled and lut contents are unknown. after program and verify operations are finished, in order to enable lut translations, set the lutprog bit to 0 and set the respective lut enable bits (red_lut_en, grn_lut_en, blu_lut_en) to 1 to enable the desired lut translation function. only the selected colors are translated by the lut (the other colors are not touched). the c does not need to fill in all three color lookup tables if all three color translations are not needed. after a pixel is deserialized, decoded, and decrypted (if necessary), it is segmented into its color components red, green, and blue (rgb) according to table 13 and figure 56 . if lut translation is enabled, each 8-bit pretranslation color value is used as address to the respective lut table to look up the corresponding (translated) 8-bit color value. table 13. pixel data format table 12. configuration input map cx/tp function high coax+ input. 7-bit device address is xxxxxx0 (bin). mid coax- input. 7-bit device address is xxxxxx1 (bin). low twisted-pair input. 7-bit device address is xxxxxx0 (bin). dout [5:0] dout [11:6] dout [17:12] dout18 dout19 dout20 dout [22:21] dout [24:23] dout [26:25] r[5:0] g[5:0] b[5:0] hs vs de r[7:6] g[7:6] b[7:6] downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 70 lut bit width in 32-bit and high-bandwidth modes, 24 bits are available for color data (8 bits per color) and each lut is used for 8-bit to 8-bit color translation. in 24-bit mode, the deserializer can receive only up to 18-bit color (6 bits per color). the lut tables can translate from 6-bit to 6-bit, using the first 64 locations (0x00 to 0x3f). program the msb 2 bits of each lut value to 00. alternatively, pro- gram full 8-bit values to each lut for 6-bit to 8-bit color translation. recommended lut program procedure 1) write lutprog = 1 to register 0x7c. keep bluluten = 0, grnluten = 0, redluten = 0 (write 0x08 to register 0x7c). 2) write contents of red lut with a single write packet. for 24-bit rgb, use 0x7d as register address and 0x00 as number of bytes (uart only) and write 256 bytes. for 18-bit rgb, use 0x7d as register address and 0x40 as number of bytes (uart only) and write 64 bytes. (optional: multiple write packets can be used if lutaddr is set before each lut write packet.) 3) read contents of red lut and verify that they are correct. use the same register address and number of bytes used in the previous step. 4) repeat steps 2 and 3 for the green lut, using 0x7e as the register address. 5) repeat steps 2 and 3 for the blue lut, using 0x7f as the register address. 6a) to finish the program and verify routine, without enabling the lut color translation, write lutprog = 0 (write 0x00 to register 0x7c). 6b) to finish the program and verify routine, and start lut color translation, write lutprog = 0, bluluten = 1, grnluten = 1, redluten = 1 (write 0x07 to register 0x7c). figure 56. lut dataflow addr r5 r4 r3 r2 r1 r0 24-bit mode 32-bit or high- bandwidth mode r7 r6 0 0 red lut data msb lsb msb lsb dout3 dout9 dout8 dout7 dout6 dout2 dout1 dout0 dout4 dout5 r5 r4 r3 r2 r1 r0 r6 r7 addr g5 g4 g3 g2 g1 g0 g7 g6 0 0 green lut data msb lsb msb lsb g5 g4 g3 g2 g1 g0 g6 g7 addr b5 b4 b3 b2 b1 b0 b7 b6 0 0 blue lut data msb lsb msb lsb b5 b4 b3 b2 b1 b0 b6 b7 en redluten en grnluten en bluluten dout 22 dout 24 dout 26 dout 25 dout 17 dout 16 dout 15 dout 14 dout 13 dout 12 dout 23 dout 11 dout 10 dout 21 output pin output signal 24-bit mode 32-bit or high- bandwidth mode 24-bit mode 32-bit or high- bandwidth mode downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 71 high-immunity reverse control-channel mode the deserializer contains a high-immunity reverse control-channel mode, which has increased robustness at half the bit rate over the standard gmsl reverse control- channel link ( table 14 ). connect a 30k resistor to gpo/ him on the serializer, and sd/him on the deserializer to use high-immunity mode at power-up. set the highimm bit high in both the serializer and deserializer to enable high-immunity mode at any time after power-up. set the highimm bit low in both the serializer and deserializer to use the legacy reverse control-channel mode. the deserializer reverse channel mode is not available for 500s/1.92ms after the reverse control-channel mode is changed through the serializer/deserializers highimm bit setting, respectively. the user must set sd/him and gpo/him or the highimm bits to the same value for proper reverse control-channel communication. in high-immunity mode, set hpftune = 00 in the equal- izer, if the serial bit rate = [pixel clock x 30 (bws = low or open) or 40 (bws = high)] is larger than 1gbps when bws is low or high. when bws = open, set hpftune = 00 when the serial bit rate is larger than 2gbps. in addi- tion, use 47nf ac-coupling capacitors. note that legacy reverse control-channel mode may not function when using 47nf ac-coupling capacitors. by default, high-immunity mode uses a 500kbps bit rate. set revfast =1 (d7 in register 0x1a in the serializer and register 0x11 in the deserializer) in both devices to use a 1mbps bit rate. certain limitations apply when using the fast high-immunity mode ( table 15 ). sleep mode the deserializers have sleep mode to reduce power consumption. the devices enter or exit sleep mode by a command from a remote c using the control channel. set the sleep bit to 1 to initiate sleep mode. entering sleep mode resets the hdcp registers, but not the con- figuration registers. the deserializer sleeps after serial link inactivity or 8ms (whichever arrives first) after setting its sleep = 1. see the link startup procedure section for details on waking up the device for different c and starting conditions. to wake up from the local side, send an arbitrary control- channel command to the deserializer, wait for 5ms for the chip to power up, and then write 0 to sleep register bit to make the wake-up permanent. to wake up from the remote side, enable serialization. the deserializer detects the activity on serial link and then when it locks, it auto- matically sets its sleep register bit to 0. power-down mode the deserializers have a power-down mode that further reduces power consumption compared to sleep mode. set pwdn low to enter power-down mode. in power-down, the parallel outputs remain high impedance. entering power- down resets the devices registers. upon exiting power- down, the state of external pins add0Cadd2, cx/tp, i2csel, drs, eqs, him/cntl1, and bws are latched. table 14. reverse control-channel modes table 15. fast high-immunity mode requirements fast high-immunity mode requires drs = 0. x = dont care. highimm bit or sd/him pin setting revfast bit reverse control-channel mode max uart/ i 2 c bit rate (kbps) low (0) x legacy reverse control-channel mode (compatible with all gmsl devices) 1000 high (1) 0 high-immunity mode 500 1 fast high-immunity mode 1000 bws setting allowed pixel clock frequency (mhz) low > 41.66 high > 30 open > 83.33 downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 72 coniguration link the control channel can operate in a low-speed mode called configuration link in the absence of a clock input. this allows a microprocessor to program configuration registers before starting the video link. an internal oscil- lator provides the clock for the configuration link. set clinken = 1 on the serializer to enable configuration link. configuration link is active until the video link is enabled. the video link overrides the configuration link and attempts to lock when seren = 1. link startup procedure table 16 lists the startup procedure for image-sensing applications. the control channel is available after the video link or the configuration link is established. if the deserializer powers up after the serializer, the control channel becomes unavailable for 2ms after power-up. table 16. startup procedure for image-sensing applications (cds = high, figure 58) no. c serializer deserializer (autostart enabled) (autostart disabled) c connected to deserializer. sets all coniguration inputs. sets all coniguration inputs. sets all coniguration inputs. 1 powers up. powers up and loads default settings. establishes video link when valid pclk available. powers up and loads default settings. goes to sleep after 8ms. powers up and loads default settings. locks to video link signal if available. 2 writes deserializer coniguration bits and gets an acknowledge. coniguration changed from default settings. 3 wakes up the serializer by sending dummy packet, and then writing sleep = 0 within 8ms. may not get an acknowledge (or gets a dummy acknowledge) if not locked. wakes up. 4 writes serializer coniguration bits. may not get an acknowledge (or gets a dummy acknowledge) if not locked. coniguration changed from default settings. 5 if not already enabled, sets seren = 1, gets an acknowledge and waits for serial link to be established (~3ms). establishes video link when valid pclk available (if not already enabled). locks to video link signal (if not already locked). 6 begin sending video data to input. video data serialized and sent across serial link. video data received and deserialized. downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 73 high-bandwidth digital content protection (hdcp) note: the explanation of hdcp operation in this data sheet is provided as a guide for general understanding. implementation of hdcp in a product must meet the requirements given in the hdcp system v1.3 amendment for gmsl, which is available from dcp. hdcp has two main phases of operation, authentication and the link integrity check. the c starts authentica- tion by writing to the start_authentication bit in the gmsl serializer. the gmsl serializer generates a 64-bit random number. the host c first reads the 64-bit random number from the gmsl serializer and writes it to the deserializer. the c then reads the gmsl serial- izer public key selection vector (aksv) and writes it to the deserializer. the c then reads the deserializer ksv (bksv) and writes it to the gmsl serializer. the c begins checking bksv against the revocation list. using the cipher, the gmsl serializer and deserializer calculate a 16-bit response value, r0 and r0, respectively. the gmsl amendment for hdcp reduces the 100ms mini- mum wait time allowed for the receiver to generate r0 (specified in hdcp rev 1.3) to 128 pixel clock cycles in the gmsl amendment. there are two response-value comparison modes, internal comparison and c comparison. set en_int_comp = 1 to select internal comparison mode. set en_int_comp = 0 to select c comparison mode. in internal compari- son mode, the c reads the deserializer response r0 and writes it to the gmsl serializer. the gmsl serializer compares r0 to its internally generated response value r0, and sets r0_ri_matched. in c comparison mode, the c reads and compares the r0/r0 values from the gmsl serializer/deserializer. during response-value generation and comparison, the host c checks for a valid bksv (having 20 1s and 20 0s is also reported in bksv_invalid) and checks bksv against the revocation list. if bksv is not on the list and the response values match, the host authenticates the link. if the response values do not match, the c resam- ples the response values (as described in hdcp rev 1.3, appendix c). if resampling fails, the c restarts authen- tication by setting the reset_hdcp bit in the gmsl serializer. if bksv appears on the revocation list, the host cannot transmit data that requires protection. the host knows when the link is authenticated and decides when to output data requiring protection. the c performs a link integrity check every 128 frames or every 2s 0.5s. the gmsl serializer/deserializer generate response values every 128 frames. these values are compared internally (internal comparison mode) or can be compared in the host c. in addition, the gmsl serializer/deserializer provide response values for the enhanced link verification. enhanced link verification is an optional method of link verification for faster detection of loss-of-synchronization. for this option, the gmsl serializer and deserializer generate 8-bit enhanced link-verification response values (pj and pj) every 16 frames. the host must detect three consecutive pj/pj mismatches before resampling. encryption enable the gmsl link transfers either encrypted or nonen- crypted data. to encrypt data, the host c sets the encryption enable (encryption_enable) bit in both the gmsl serializer and deserializer. the c must set encryption_enable in the same vsync cycle in both the gmsl serializer and deserializer (no internal vsync falling edges between the two writes). the same timing applies when clearing encryption_enable to disable encryption. note: encryption_enable enables/disables encryp- tion on the gmsl irrespective of the content. to comply with hdcp, the c must not allow content requiring encryption to cross the gmsl unencrypted. the c must complete the authentication process before enabling encryption. in addition, encryption must be dis- abled before starting a new authentication session. synchronization of encryption the video vertical sync (vsync) synchronizes the start of encryption. once encryption has started, the gmsl generates a new encryption key for each frame and each line, with the internal falling edge of vsync and hsync. rekeying is transparent to data and does not disrupt the encryption of video or audio data. repeater support the gmsl serializer/deserializer include features to build an hdcp repeater. an hdcp repeater receives and decrypts hdcp content and then encrypts and transmits on one or more downstream links. a repeater can also use decrypted hdcp content (e.g., to display on a screen). to support hdcp repeater-authentication protocol, the deserializer has a repeater register bit. this register bit must be set to 1 by a c (most likely on the repeater module). both the gmsl serializer and deserializer use sha-1 hash-value calculation over the assembled ksv lists. hdcp gmsl links support a maximum of 15 receiv- ers (total number including the ones in repeater modules). downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 74 if the total number of downstream receivers exceeds 14, the c must set the max_devs_exceeded register bit when it assembles the ksv list. hdcp authentication procedures the gmsl serializer generates a 64-bit random number exceeding the hdcp requirement. the gmsl serial- izer/deserializer internal one-time programmable (otp) memories contain a unique hdcp keyset programmed at the factory. the host c initiates and controls the hdcp authentication procedure. the gmsl serializer and dese- rializer generate hdcp authentication response values for the verification of authentication. use the following procedures to authenticate the hdcp gmsl encryption (refer to the hdcp 1.3 amendment for gmsl for details). the c must perform link integrity checks while encryp- tion is enabled (see table 17 ). any event that indicates that the deserializer has lost link synchronization should retrigger authentication. the c must first write 1 to the reset_hdcp bit in the gmsl serializer before starting a new authentication attempt. hdcp protocol summary table 17 , table 18 , and table 19 list the summaries of the hdcp protocol. these tables serve as an implementation guide only. meet the requirements in the gmsl amend- ment for hdcp to be in full compliance. table 17. startup, hdcp authentication, and normal operation (deserializer is not a repeater)first part of the hdcp authentication protocol no. c hdcp gmsl serializer hdcp gmsl deserializer 1 initial state after power-up. powers up waiting for hdcp authentication. powers up waiting for hdcp authentication. 2 makes sure that a/v data not requiring protection (low-value content) is available at the gmsl serializer inputs (such as blue or informative screen). alternatively, uses the force_video and force_audio bits of the gmsl serializer to mask a/v data at the input of the gmsl serializer. starts the link by writing seren = h or link starts automatically if autos is low. 3 starts serialization and transmits low-value content a/v data. locks to incoming data stream and outputs low-value content a/v data. 4 reads the locked bit of the deserializer and makes sure the link is established. 5 optionally writes a random-number seed to the gmsl serializer. combines seed with internally generated random number. if no seed provided, only internal random number is used. 6 if hdcp encryption is required, starts authentication by writing 1 to the start_authentication bit of the gmsl serializer. generates (stores) an, and resets the start_authentication bit to 0. 7 reads an and aksv from the gmsl serializer and writes to the deserializer. generates r0 triggered by the cs write of aksv. 8 reads the bksv and repeater bit from the deserializer and writes to the gmsl serializer. generates r0, triggered by the cs write of bksv. downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 75 table 17. startup, hdcp authentication, and normal operation (deserializer is not a repeater)first part of the hdcp authentication protocol (continued) no. c hdcp gmsl serializer hdcp gmsl deserializer 9 reads the invalid_bksv bit of the gmsl serializer and continues with authentication if it is 0. authentication can be restarted if it fails (set reset_hdcp = 1 before restarting authentication). 10 reads r0 from the deserializer and reads r0 from the gmsl serializer. if they match, continues with authentication; otherwise, retries up to two more times (optionally, gmsl serializer comparison can be used to detect if r0/r0 match). authentication can be restarted if it fails (set reset_hdcp = 1 before restarting authentication). 11 waits for the vsync falling edge (internal to the gmsl serializer) and then sets the encryption_enable bit to 1 in the deserializer and gmsl serializer (if the fc is not able to monitor vsync, it can utilize the vsync_det bit in the gmsl serializer). encryption enabled after the next vsync falling edge. decryption enabled after the next vsync falling edge. 12 checks that bksv is not in the key revocation list and continues if it is not. authentication can be restarted if it fails. note: revocation list check can start after bksv is read in step 8. 13 starts transmission of a/v content that needs protection. performs hdcp encryption on high-value content a/v data. performs hdcp decryption on high- value content a/v data. downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 76 table 18. link integrity check (normal)performed every 128 frames after encryption is enabled no. c hdcp gmsl serializer hdcp gmsl deserializer 1 generates ri and updates the ri register every 128 vsync cycles. generates ri and updates the ri register every 128 vsync cycles. 2 continues to encrypt and transmit a/v data. continues to receive, decrypt, and output a/v data. 3 every 128 video frames (vsync cycles) or every 2s. 4 reads ri from the gmsl serializer. 5 reads ri from the deserializer. 6 reads ri again from the gmsl serializer and makes sure it is stable (matches the previous ri that it has read from the gmsl serializer). if ri is not stable, go back to step 5. 7 if ri matches ri, the link integrity check is successful; go back to step 3. 8 if ri does not match ri, the link integrity check fails. after the detection of failure of link integrity check, the fc makes sure that a/v data not requiring protection (low-value content) is available at the gmsl serializer inputs (such as blue or informative screen). alternatively, the force_video and force_audio bits of the gmsl serializer can be used to mask a/v data input of the gmsl serializer. 9 writes 0 to the encryption_enable bit of the gmsl serializer and deserializer. disables encryption and transmits low-value content a/v data. disables decryption and outputs low- value content a/v data. 10 restarts authentication by writing 1 to the reset_hdcp bit followed by writing 1 to the start_authentication bit in the gmsl serializer. downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 77 table 19. optional enhanced link integrity checkperformed every 16 frames after encryption is enabled no. c hdcp gmsl serializer hdcp gmsl deserializer 1 generates pj and updates the pj register every 16 vsync cycles. generates pj and updates the pj register every 16 vsync cycles. 2 continues to encrypt and transmit a/v data. continues to receive, decrypt, and output a/v data. 3 every 16 video frames, reads pj from the gmsl serializer and pj from the deserializer. 4 if pj matches pj, the enhanced link integrity check is successful; go back to step 3. 5 if there is a mismatch, retry up to two more times from step 3. enhanced link integrity check fails after 3 mismatches. after the detection of failure of enhanced link integrity check, the c makes sure that a/v data not requiring protection (low-value content) is available at the gmsl serializer inputs (such as blue or informative screen). alternatively, the force_video and force_audio bits of the gmsl serializer can be used to mask a/v data input of the gmsl serializer. 6 writes 0 to the encryption_enable bit of the gmsl serializer and deserializer. disables encryption and transmits low-value content a/v data. disables decryption and outputs low- value content a/v data. 7 restarts authentication by writing 1 to the reset_hdcp bit followed by writing 1 to the start_authentication bit in the gmsl serializer. downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 78 example repeater networktwo cs the example shown in figure 58 has one repeater and two cs. table 20 summarizes the authentication operation. detection and action upon new device connection when a new device is connected to the system, the device must be authenticated and the devices ksv checked against the revocation list. the downstream cs can set the new_dev_conn bit of the upstream receiver and invoke an interrupt to notify upstream cs. figure 57. state diagram (cds = high) figure 58. example network with one repeater and two cs (tx = gmsl serializers, rx = deserializers) sleep config link operating program registers power-off high to low sleep = 1, video link or config link not locked after 8ms power-on idle wake-up signal serial port locking signal detected config link unlocked config link locked video link locked video link unlocked 0 sleep 0 sleep all states gpi changes from low to high or pwdn = low or send gpi to gmsl serializer pwdn = high,power-on power-down or power-off serial link activity stops or 8ms elapses after c sets sleep = 1 video link operating prbsen = 0prbsen = 1 video link prbs test bd-drive rx_r1 c_b tx_b1 display 1 rx_d1 display 2 rx_d2 repeater tx_r1 tx_r2 rx_r2 c_r video routing memory with srm video connectioncontrol connection 1 (c_b in bd-drive is master) control connection 2 (c_r in repeater is master) downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 79 table 20. hdcp authentication and normal operation (one repeater, two cs)first and second parts of the hdcp authentication protocol no. c_b c_r hdcp gmsl serializer (tx_b1, tx_r1, tx_r2) hdcp gmsl deserializer (rx_r1, rx_d1, rx_d2) tx_b1 cds = 0tx_r1 cds = 0 tx_r2 cds = 0 rx_r1 cds = 1rx_d1 cds = 0 rx_d2 cds = 0 1 initial state after power-up. initial state after power-up. all: power-up waiting for hdcp authentication. all: power-up waiting for hdcp authentication. 2 writes repeater = 1 in rx_r1. retries until proper acknowledge frame received. note: this step must be completed before the irst part of authentication is started between tx_b1 and rx_r1 by the c_b (step 7). for example, to satisfy this requirement, rx_r1 can be held at power-down until c_r is ready to write the repeater bit, or c_b can poll c_r before starting authentication. 3 makes sure that a/v data not requiring protection (low- value content) is available at the tx_b1 inputs (such as blue or informative screen). alternatively, the force_ video and force_audio bits of tx_b1 can be used to mask a/v data input of tx_b1. starts the link between tx_b1 and rx_r1 by writing seren = h to tx_b1, or link starts automatically if serializers autos is low. tx_b1: starts serialization and transmits low-value content a/v data. rx_r1: locks to incoming data stream and outputs low-value content a/v data. 4 starts all downstream links by writing seren = h to tx_r1, tx_r2, or links start automatically if autos of transmitters are low. tx_r1, tx_r2: starts serialization and transmits low-value content a/v data. rx_d1, rx_d2: locks to incoming data stream and outputs low-value content a/v data. downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 80 table 20. hdcp authentication and normal operation (one repeater, two cs)first and second parts of the hdcp authentication protocol (continued) no. c_b c_r hdcp gmsl serializer (tx_b1, tx_r1, tx_r2) hdcp gmsl deserializer (rx_r1, rx_d1, rx_d2) tx_b1 cds = 0tx_r1 cds = 0 tx_r2 cds = 0 rx_r1 cds = 1rx_d1 cds = 0 rx_d2 cds = 0 5 reads the locked bit of rx_r1 and makes sure the link between tx_b1 and rx_r1 is established. reads the locked bit of rx_d1 and makes sure the link between tx_r1 and rx_d1 is established. reads the locked bit of rx_d2 and makes sure the link between tx_r2 and rx_d2 is established. 6 optionally, writes a random number seed to tx_b1. writes 1 to the gpio_0_function and gpio_1_function bits in rx_r1 to change gpio functionality used for hdcp purpose. optionally, writes a random-number seed to tx_r1 and tx_r2. 7 starts and completes the irst part of the authentication protocol between tx_b1, rx_r1 (see steps 6C10 in table 18). tx_b1: according to commands from c_b, generates an, computes r0. rx_r1: according to commands from c_b, computes r0. 8 when gpio_1 = 1 is detected, starts and completes the irst part of the authentication protocol between the (tx_r1, rx_d1) and (tx_r2, rx_d2) links (see steps 6C10 in table 18). tx_r1, tx_r2: according to commands from c_r, generates an, computes r0. rx_d1, rx_d2: according to commands from c_r, computes r0. 9 waits for the vsync falling edge and then enables encryption on the (tx_b1, rx_r1) link. full authentication is not complete yet so it makes sure a/v content that needs protection is not transmitted. since repeater = 1 was read from rx_r1, the second part of authentication is required. tx_b1: encryption enabled after next vsync falling edge. rx_r1: decryption enabled after next vsync falling edge. downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 81 table 20. hdcp authentication and normal operation (one repeater, two cs)first and second parts of the hdcp authentication protocol (continued) no. c_b c_r hdcp gmsl serializer (tx_b1, tx_r1, tx_r2) hdcp gmsl deserializer (rx_r1, rx_d1, rx_d2) tx_b1 cds = 0tx_r1 cds = 0 tx_r2 cds = 0 rx_r1 cds = 1rx_d1 cds = 0 rx_d2 cds = 0 10 when gpio_0 = 1 is detected, enables encryption on the (tx_r1, rx_d1) and (tx_r2, rx_d2) links. tx_r1, tx_r2: encryption enabled after next vsync falling edge. rx_d1, rx_d2: decryption enabled after next vsync falling edge. 11 waits for some time to allow c_r to make the ksv list ready in rx_r1. then polls (reads) the ksv_list_ready bit of rx_r1 regularly until proper acknowledge frame is received and bit is read as 1. blocks control channel from c_b side by setting revccen = fwdccen = 0 in rx_r1. retries until proper acknowledge frame received. rx_r1: control channel from serializer side (tx_b1) is blocked after fwdccen = revccen = 0 is written. 12 writes bksvs of rx_d1 and rx_d2 to the ksv list in rx_ r1. then, calculates and writes the binfo register of rx_r1. rx_r1: triggered by c_rs write of binfo, calculates hash value (v) on the ksv list, binfo and the secret- value m0. 13 writes 1 to the ksv_list_ ready bit of rx_r1 and then unblocks the control channel from the c_b side by setting revccen = fwdccen = 1 in rx_r1. rx_r1: control channel from the serializer side (tx_b1) is unblocked after fwdccen = revccen = 1 is written. 14 reads the ksv list and binfo from rx_r1 and writes them to tx_b1. if any of the max_ devs_exceeded or max_ cascade_exceeded bits is 1, then authentication fails. note: binfo must be written after the ksv list. tx_b1: triggered by c_bs write of binfo, calculates hash value (v) on the ksv list, binfo and the secret- value m0. 15 reads v from tx_b1 and v from rx_r1. if they match, continues with authentication; otherwise, retries up to two more times. 16 searches for each ksv in the ksv list and bksv of rx_r1 in the key revocation list. downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 82 notiication of start of authentication and enable of encryption to downstream links hdcp repeaters do not immediately begin authentication upon startup or detection of a new device, but instead wait for an authentication request from the upstream transmit- ter/repeaters. use the following procedure to notify downstream links of the start of a new authentication request: 1) host c begins authentication with the hdcp repeaters input receiver. 2) when aksv is written to hdcp repeaters input receiver, its auth_started bit is automatically set and its gpio1 goes high (if gpio1_function is set to high). 3) hdcp repeaters c waits for a low-to-high transition on hdcp repeater input receivers auth_started bit and/or gpio1 (if configured) and starts authentica- tion downstream. 4) hdcp repeaters c resets the auth_started bit. set gpio0_function to high to have gpio0 follow the encryption_enable bit of the receiver. the repeater c can use this function for notification when encryption is enabled/disabled by an upstream c. applications information self prbs test the serializers include a prbs pattern generator that works with bit-error verification in the deserializer. to run the prbs test, first disable hdcp encryption. next, set dishsfilt, disvsfilt, and disdefilt to 1, to disable glitch filter in the deserializer. then, set prbsen = 1 (0x04, d5) in the serializer and then in the deserializer. to exit the prbs test, set prbsen = 0 (0x04, d5) in the deserializer and then in the serializer. error checking the deserializers check the serial link for errors and store the number of decoding errors in the 8-bit registers decerr (0x0d). if a large number of decoding errors are detected within a short duration (error rate 1/4), the deserializers lose lock and stop the error counter. the deserializers then attempt to relock to the serial data. decerr reset upon successful video link lock, successful readout of the register (through c), or when- ever auto error reset is enabled. the deserializers use a separate prbs register during the internal prbs test, and decerr are reset to 0x00. err output the deserializers have an open-drain err output. this output asserts low whenever the number of decoding errors exceeds the error thresholds during normal opera- tion, or when at least one prbs error is detected during prbs test. err reasserts high whenever decerr resets, due to decerr readout, video link lock, or auto error reset. table 20. hdcp authentication and normal operation (one repeater, two cs)first and second parts of the hdcp authentication protocol (continued) no. c_b c_r hdcp gmsl serializer (tx_b1, tx_r1, tx_r2) hdcp gmsl deserializer (rx_r1, rx_d1, rx_d2) tx_b1 cds = 0tx_r1 cds = 0 tx_r2 cds = 0 rx_r1 cds = 1rx_d1 cds = 0 rx_d2 cds = 0 17 if keys are not revoked, the second part of the authentication protocol is completed. 18 starts transmission of a/v content that needs protection. all: perform hdcp encryption on high- value a/v data. all: perform hdcp decryption on high- value a/v data. downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 83 auto error reset the default method to reset errors is to read the respec- tive error registers in the deserializers (0x0d and 0x0e). auto error reset clears the error counters decerr and the err output ~1s after err goes low. auto error reset is disabled on power-up. enable auto error reset through autorst (0x06, d5). auto error reset does not run when the device is in prbs test mode. dual c control usually systems have one microcontroller to run the control channel, located on the serializer side for display applications or on the deserializer side for image-sensing applications. however, a c can reside on each side simultaneously and trade off running the control channel. in this case, each c can communicate with the serializer and deserializer and any peripheral devices. contention occurs if both cs attempt to use the control channel at the same time. it is up to the user to prevent this contention by implementing a higher level protocol. in addition, the control channel does not provide arbitration between i 2 c masters on both sides of the link. an acknowledge frame is not generated when communication fails due to contention. if communication across the serial link is not required, the cs can disable the forward and reverse control channel using the fwdccen and revccen bits (0x04, d[1:0]) in the serializer/deserializer. communication across the serial link is stopped and contention between cs cannot occur. as an example of dual c use in an image-sensing appli- cation, the serializer can be in sleep mode and waiting for wake-up by c on the deserializer side. after wake- up, the serializer-side c assumes master control of the serializers registers. changing the clock frequency it is recommended that the serial link be enabled after the video clock (f pixel ) and the control-channel clock (f uart / f i2c ) are stable. when changing the clock frequency, stop the video clock for 5s, apply the clock at the new frequency, then restart the serial link or toggle seren. on-the-fly changes in clock frequency are possible if the new frequency is immediately stable and without glitches. the reverse control channel remains unavailable for 500s after serial link start or stop. when using the uart interface, limit on-the-fly changes in f uart to factors of less than 3.5 at a time to ensure that the device recognizes the uart sync pattern. for example, when lowering the uart frequency from 1mbps to 100kbps, first send data at 333kbps then at 100kbps for reduction ratios of 3 and 3.333, respectively. spread-spectrum clock tracking using a spread-spectrum clock source can reduce emi/ emc on the serial and mipi data. the deserializer can track a spread-spectrum signal from the serializer. use a spread < 1% for csi-2 output rates 400mhz. use a spread < 0.5% for csi-2 output rates > 400mhz. fast detection of loss-of-synchronization a measure of link quality is the recovery time from loss- of-synchronization. the host can be quickly notified of loss-of-lock by connecting the deserializers lock out- put to the gpi input. if other sources use the gpi input, such as a touch-screen controller, the c can implement a routine to distinguish between interrupts from loss- of-sync and normal interrupts. reverse control-channel communication does not require an active forward link to operate and accurately tracks the lock status of the gmsl link. lock asserts for video link only and not for the configuration link. providing a frame sync (camera applications) the gpi/gpo provide a simple solution for camera applications that require a frame sync signal from the ecu (e.g., surround-view systems). connect the ecu frame sync signal to the gpi input, and connect gpo output to the camera frame sync input. gpi/gpo has a typical delay of 275s. skew between multiple gpi/ gpo channels is typically 115s. if a lower skew signal is required, connect the cameras frame sync input to one of the deserializers gpios and use an i 2 c broadcast write command to change the gpio output state. this has a maximum skew of 1.5s, independent from the used i 2 c bit rate. software programming of the device addresses the serializers and deserializers have programmable device addresses. this allows multiple gmsl devices, along with i 2 c peripherals, to coexist on the same control channel. the serializer device address is in register 0x00 of each device, while the deserializer device address is in register 0x01 of each device. to change a device address, first write to the device whose address changes (register 0x00 of the serializer for serializer device address change, or register 0x01 of the deserializer for deserializer device address change). then write the same address into the corresponding register on the other device (register 0x00 of the deserializer for serializer device address change, or register 0x01 of the serializer for deserializer device address change). downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 84 three-level coniguration inputs cx/tp and bws are three-level inputs that control the seri - al interface configuration and power-up defaults. connect three-level inputs through a pullup resistor to iovdd to set a high level, a pulldown resistor to gnd to set a low level, or open to set a mid level. for digital control, use three- state logic to drive the three-level logic input. coniguration blocking the deserializers can block changes to registers. set cfgblock to make registers 0x00 to 0x1f as read only. once set, the registers remain blocked until the supplies are removed or until pwdn is low. compatibility with other gmsl devices the deserializers are designed to pair with the max9275C max9281 serializers, but interoperate with any gmsl serializers. see table 21 for operating limitations key memory each device has a unique hdcp key set that is stored in secure nonvolatile memory (nvm). the hdcp key set consists of 40 56-bit private keys and one 40-bit public key. the nvm is qualified for automotive applications. hs/vs/de inversion the deserializers use an active-high hs, vs, and de for encoding and hdcp encryption. set invhsync, invvsync, and invde in the serializer (registers 0x0d, 0x0e) to invert active-low input signals for use with the gmsl devices. set invhsync, invvsync, and invde in the deserializer (register 0x0e) to output active-low signals for use with downstream devices. ws/sck inversion the deserializers use standard polarities for i 2 s. set invws and invsck in the serializer (register 0x1b) to invert opposite polarity signals for use with the gmsl devices. set invws and invsck in the deserializer (register 0x1d) to output reverse-polarity signals for downstream use. gpios the deserializers have two open-drain gpios available when not used for hdcp purposes (see the notification of start of authentication and enable of encryption to downstream links section), gpio1out and gpio0out (0x06, d3 and d1) set the output state of the gpios. setting the gpio output bits to 0 low pulls the output low, while setting the bits to 1 leaves the output undriven, and pulled high through internal/external pullup resistors. the gpio input buffers are always enabled. the input states are stored in gpio1 and gpio0 (0x06, d2 and d0). set gpio1out/gpio0out to 1 when using gpio1/gpio0 as an input. line-fault detection the line-fault detector monitors for line failures such as short to ground, short to battery, and open link for system-fault diagnosis. figure 1 shows the required external resistor connections. lflt = low when a line fault is detected and lflt goes high when the line returns to normal. the line-fault type is stored in 0x08 d[3:0] of the serializer. filter lflt with the c to reduce the detectors susceptibility to short ground shifts. the fault-detector threshold voltages are referenced to the serializer ground. additional passive components set the dc level of the cable. if the serializer and gmsl deserializer grounds are different, the link dc voltage during normal operation can vary and cross one of the fault-detection thresholds. table 21. max9288/max9290 feature compatibility feature gmsl serializer hdcp (max9290 only) if feature not supported in serializer, must not be turned on in the max9290. high-bandwidth mode if feature not supported in serializer, must only use 24-bit and 32-bit modes. i 2 c-to-i 2 c if feature not supported in serializer, must use uart-to-i 2 c or uart-to-uart. coax if feature not supported in serializer, must connect unused serial output through 200nf and 50 in series to v dd and set the reverse control channel amplitude to 100mv. high-immunity control channel if feature not supported in serializer, must use the legacy reverse con trol-channel mode.tdm encoding if feature not supported in serializer, must use i 2 s encoding (with 50% ws duty cycle), if supported. i 2 s encoding if feature not supported in serializer, must disable i 2 s in the max9288/max9290. downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 85 for the fault-detection circuit, select the resistors power rating to handle a short to the battery. in coax mode, leave the unused line-fault inputs unconnected. to detect the short-together case, refer to application note 4709: gmsl line-fault detection . table 23 lists the mapping for line fault types internal input pulldowns the control and configuration inputs (except three-level inputs) include a pulldown resistor to gnd. external pulldown resistors are not needed. choosing i 2 c/uart pullup resistors i 2 c and uart open-drain lines require a pullup resistor to provide a logic-high level. there are tradeoffs between power dissipation and speed, and a compromise may be required when choosing pullup resistor values. every device connected to the bus introduces some capacitance even when the device is not in operation. i 2 c specifies 300ns rise times (30% to 70%) for fast mode, which is defined for data rates up to 400kbps (see the i 2 c specifications in the ac electrical characteristics table for details). to meet the fast-mode rise-time requirement, choose the pullup resistors so that rise time t r = 0.85 x r pullup x c bus < 300ns. the waveforms are not recognized if the transition time becomes too slow. the device supports i 2 c/uart rates up to 1mbps. ac-coupling ac-coupling isolates the receiver from dc voltages up to the voltage rating of the capacitor. capacitors at the serializer output and at the deserializer input are needed for proper link operation and to provide protection if either end of the cable is shorted to a battery. ac-coupling blocks low-frequency ground shifts and low-frequency common-mode noise. selection of ac-coupling capacitors voltage droop and the digital sum variation (dsv) of transmitted symbols cause signal transitions to start from different voltage levels. because the transition time is fixed, starting the signal transition from different voltage levels causes timing jitter. the time constant for an ac-coupled link needs to be chosen to reduce droop and jitter to an acceptable level. the rc network for an ac-coupled link consists of the cml/coax receiver termination resistor (r tr ), the cml/coax driver termination resistor (r td ), and the series ac-coupling capacitors (c). the rc time constant for four equal-value series capacitors is (c x (r td + r tr ))/4. r td and r tr are required to match the transmission line impedance (usually 100 differential, 50 single ended). this leaves the capacitor selection to change the system time constant. use at 0.22f (using legacy reverse control channel), 47nf (using high-immunity reverse control channel), or larger high-frequency surface-mount ceramic capacitors, with sufficient voltage rating to withstand a short to battery, to pass the lower speed reverse control-channel signal. use capacitors with a case size less than 3.2mm x 1.6mm to have lower parasitic effects to the high-speed signal. power-supply circuits and bypassing the deserializers use an avdd18 and dvdd18 of 1.7v to 1.9v and an avdd3 of 3.0v to 3.6v. all single-ended inputs and outputs except for the serial input derive power from an iovdd of 1.7v to 3.6v that scale with iovdd. proper voltage-supply bypassing is essential for high- frequency circuit stability. power-supply table power-supply currents shown in the dc electrical characteristics table is measured at v iovdd = 3.6v. if using a different iovdd voltage, the iovdd worst-case supply current will vary. hdcp operation (max9290 only) draws additional current. this is shown in table 24 . cables and connectors interconnect for cml typically has a differential impedance of 100. use cables and connectors that have matched differential impedance to minimize imped- ance discontinuities. coax cables typically have a characteristic impedance of 50, contact the factory for 75 operation). table 24 lists the suggested cables and connectors used in the gmsl link. board layout separate lvcmos logic signals and cml/coax high- speed signals to prevent crosstalk. use a four-layer pcb with separate layers for power, ground, cml/coax, and lvcmos logic signals. layout pcb traces close to each other for a 100 differential characteristic impedance for stp. the trace dimensions depend on the type of trace used (microstrip or stripline). note that two 50 pcb traces do not have 100 differential impedance when brought close togetherthe impedance goes down when the traces are brought closer. use a 50 trace for the single-ended output when driving coax. route the pcb traces for differential cml channel in parallel to maintain the differential characteristic imped- ance. avoid vias. keep pcb traces that make up a differential pair equal length to avoid skew within the differential pair. downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 86 table 22. line-fault mapping table 23. additional supply current from hdcp (max9290 only) table 24. suggested connectors and cables for gmsl register address bits name value line-fault type 0x76 d[3:2] lfneg 00 negative cable wire shorted to supply voltage 01 negative cable wire shorted to ground 10 normal operation 11 negative cable wire disconnected d[1:0] lfpos 00 positive cable wire shorted to supply voltage 01 positive cable wire shorted to ground 10 normal operation 11 positive cable wire disconnected pixel clock (mhz) maximum hdcp current (ma) 16.6 6 33.3 9 36.6 9 66.6 12 104 18 vendor connector cable type rosenberger 59s2ax-400a5-y rg174 coax rosenberger d4s10a-40ml5-z dacar 538 stp nissei gt11l-2s f-2wme awg28 stp jae mx38-ff a-bw-lxxxxx stp downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 87 esd protection esd tolerance is rated for human body model, iec 61000-4-2, and iso 10605. the iso 10605 and iec 61000-4-2 standards specify esd tolerance for electronic systems. the serial link inputs are rated for iso 10605 esd protection and iec 61000-4-2 esd protection. all pins are tested for the human body model. the human body model discharge components are c s = 100pf and r d = 1.5k ( figure 59 ). the iec 61000-4-2 discharge components are c s = 150pf and r d = 330 ( figure 60 ). the iso 10605 discharge components are c s = 330pf and r d = 2k ( figure 61 ). figure 59. human body model esd test circuit figure 60. iec 61000-4-2 contact discharge esd test circuit figure 61. iso 10605 contact discharge esd test circuit c s 150pf storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance r d 330 ? storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance 1m ? r d 1.5k ? c s 100pf storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance r d 2k ? c s 330pf downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 88 table 25. register table register address bits name value function default value 0x00 d[7:1] serid xxxxxxx serializer device address (power-up default value depends on latched address pin level). xx00xx0 d0 0 reserved 0 0x01 d[7:1] desid xxxxxxx deserializer device address (power-up default value depends on latched address pin level). xx01xxx d0 cfgblock 0 normal operation 0 1 registers 0x00 to 0x1f and 0x60 to 0x67 are read only. 0x02 d[7:6] 00 reserved 00 d5 audiomode 0 ws, sck conigured as output (deserializer-sourced clock). 0 1 ws, sck conigured as input (system-sourced clock). d4 audioen 0 disable i 2 s/tdm channel. 1 1 enable i 2 s/tdm channel. d[3:0] 1111 reserved 1111 0x03 d[7:0] 00000000 reserved 00000000 0x04 d7 locked 0 lock output is low. 0 (read only) 1 lock output is high. d6 0 reserved 0 d5 prbsen 0 disable prbs test. 0 1 enable prbs test. d4 sleep 0 normal mode (power-up default value depends on cds and ms pin value at power-up). 0, 1 1 activate sleep mode (power-up default value depends on cds and ms pin value at power-up). d[3:2] inttype 00 local control channel uses i 2 c when i2csel = 0. 01 01 local control channel uses uart when i2csel = 0. 10, 11 local control channel disabled. d1 revccen 0 disable reverse control channel to serializer (sending). 1 1 enable reverse control channel to serializer (sending). d0 fwdccen 0 disable forward control channel from serializer (receiving) 1 1 enable forward control channel from serializer (receiving). downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 89 table 25. register table (continued) register address bits name value function default value 0x05 d7 i2cmethod 0 i 2 c conversion sends the register address when converting uart-to-i 2 c. 0 1 disable sending of i 2 c register address when converting uart-to-i 2 c (command-byte-only mode). d[6:5] hpftune 00 7.5mhz equalizer highpass ilter cutoff frequency. 01 01 3.75mhz equalizer highpass ilter cutoff frequency 10 2.5mhz equalizer highpass ilter cutoff frequency. 11 1.87mhz equalizer highpass ilter cutoff frequency. d4 pdeq 0 enable equalizer. 0 1 disable equalizer. d[3:0] eqtune 0000 2.1db equalizer-boost gain. 0100,1001 0001 2.8db equalizer-boost gain. 0010 3.4db equalizer-boost gain. 0011 4.2db equalizer-boost gain. 0100 5.2db equalizer-boost gain. power-up default when eqs is high . 0101 6.2db equalizer-boost gain. 0110 7db equalizer-boost gain. 0111 8.2db equalizer-boost gain. 1000 9.4db equalizer-boost gain. 1001 10.7db equalizer-boost gain. power-up default when eqs is low . 1010 11.7db equalizer-boost gain. 1011 13db equalizer-boost gain. 11xx do not use. downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 90 table 25. register table (continued) register address bits name value function default value 0x06 d7 prbstype 0 device uses standard prbs test. 0 1 device uses max9271/max9273-compatible prbs test (for use with the max9271/ max9273 only). d6 autorst 0 do not automatically reset error registers and outputs. 0 1 automatically reset decerr register 1s after err asserts. d5 disgpi 0 enable gpi-to-gpo signal transmission to serializer. 0 1 disable gpi-to-gpo signal transmission to serializer. d4 gpiin 0 gpi input is low. 0 (read only) 1 gpi input is high. d3 gpio1out 0 set gpio1 to low. 1 1 set gpio1 to high. d2 gpio1in 0 gpio1 input is low. 0 (read only) 1 gpio1 input is high. d1 gpio0out 0 set gpio0 to low. 1 1 set gpio0 to high. d0 gpio0in 0 gpio0 input is low. 0 (read only) 1 gpio0 input is high. 0x07 d[7:0] 01010100 reserved 01010100 0x08 d[7:5] 001 reserved 001 d[4:3] hvsrc 00 d18/d19 assigned to hs/vs . 00 01 d14/d15 assigned to hs/vs (for use with the max9271). 1x d0/d1 assigned to hs/vs (d[19:2] shifted to d[17:0]). for use with the max9271/max9273 with h/v inversion). d2 disdefilt 0 enable de glitch ilter. 0 1 disable de glitch ilter. d1 disvsfilt 0 enable vs glitch ilter. 0 1 disable vs glitch ilter. d0 dishsfilt 00 enable hs glitch ilter. 0 10, 11 disable hs glitch ilter. downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 91 table 25. register table (continued) register address bits name value function default value 0x09 d7 vsyncout 0 normal cntl3 operation. 0 1 cntl3 outputs vsync. d6 autoppl 0 automatic pixel count disabled. 0 1 automatic pixel count enabled. d[5:0] 000000 reserved 000000 0x0a d[7:0] 00010xxx reserved 00010xxx 0x0b d[7:0] 00100000 reserved 00100000 0x0c d[7:0] errthr xxxxxxxx error threshold for decoding errors. 00000000 0x0d d[7:0] decerr xxxxxxxx decoding error counter. 00000000 (read only) 0x0e d[7:0] prbserr xxxxxxxx prbs error counter. 00000000 (read only) 0x0f d[7:0] xxxxxxxx reserved (read only) 0x10 d[7:0] xxxxxxxx reserved (read only) 0x11 d7 revfast 0 high-immunity reverse channel mode uses 500kbps bit rate. 0 1 high-immunity reverse channel mode uses 1mbps bit rate. d[6:0] 0100010 reserved 0100010 0x12 d7 mclksrc 0 mclk derived from pclkout. see table 9. 0 1 mclk derived from internal oscillator. d[6:0] mclkdiv 0000000 mclk disabled. 0000000 xxxxxxx mclk divider. 0x13 d[7:0] 0x000000 reserved 0x000000 downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 92 table 25. register table (continued) register address bits name value function default value 0x14 d7 invvs 0 normal vsync operation. 0 1 invert vsync. d6 invhs 0 normal hsync operation. 0 1 invert hsync. d5 invde 0 normal de operation. 0 1 invert de. d4 drs 0 high data rate mode. power-up default when drs pin is low (transitions on the drs pin override the drs bit setting). 0, 1 1 low data rate mode. power-up default when drs pin is high (transitions on the drs pin override the drs bit setting). d3 dcs 0 normal parallel output driver current. 0 1 boosted parallel output driver current. d2 disrwake 0 enable remote wake-up. 0 1 disable remote wake-up. d1 0 reserved 0 d0 intout 0 drive intout low. 0 1 drive intout high. downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 93 table 25. register table (continued) register address bits name value function default value 0x15 d7 autoint 0 intout pin output controlled by intout bit above. 1 1 writes to any avinfo bytes sets intout to high. reads to any avinfo bytes sets intout to low. d6 hvtren 0 disable hs/vs tracking (power-up default value depends on state of bws input value at power-up). 0, 1 1 enable hs/vs tracking (power-up default value depends on state of bws input value at power-up). d5 detren 0 disable de tracking (power-up default value depends on state of bws input value at power-up). 0, 1 1 enable de tracking (power-up default value depends on state of bws input value at power-up). d4 hvtrmode 0 partial periodic hs/vs and de tracking. 1 1 partial and full periodic hs/vs and de tracking. d[3:2] 00 reserved 00 d1 mclkws 0 mclk output operates normally. 0 1 ws is output from mclk (mclk mirrors ws). d0 mclkpin 0 mclk output on dout28/cntl2. 0 1 mclk output on add0/cntl0. 0x16 d7 highimm 0 legacy reverse control channel mode (power-up default value depends on him/cntl1 at power-up). 0, 1 1 high-immunity reverse control channel mode (power-up default value depends on him/ cntl1 at power-up). d[6:0] 1011010 reserved 1011010 0x17 d[7:0] 000xxxxx reserved 000xxxxx 0x18 d[7:1] i2csrca xxxxxxx i 2 c address translator source a. 0000000 d0 0 reserved 0 0x19 d[7:1] i2cdsta xxxxxxx i 2 c address translator destination a. 0000000 d0 0 reserved 0 0x1a d[7:1] i2csrcb xxxxxxx i 2 c address translator source b. 0000000 d0 0 reserved 0 downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 94 table 25. register table (continued) register address bits name value function default value 0x1b d[7:1] i2cdstb xxxxxxx i 2 c address translator destination b. 0000000 d0 0 reserved 0 0x1c d7 i2clocack 0 acknowledge not generated when forward channel is not available. 1 1 i 2 c to i 2 c-slave generates local acknowledge when forward channel is not available. d[6:5] i2cslvsh 00 352ns/117ns i 2 c setup/hold time. 01 01 469ns/234ns i 2 c setup/hold time. 10 938ns/352ns i 2 c setup/hold time. 11 1046ns/469ns i 2 c setup/hold time. d[4:2] i2cmstbt 000 8.47kbps (typ) i 2 c to i 2 c-master bit-rate setting. 101 001 28.3kbps (typ) i 2 c to i 2 c-master bit-rate setting. 010 84.7kbps (typ) i 2 c to i 2 c-master bit-rate setting. 011 105kbps (typ) i 2 c to i 2 c-master bit-rate setting. 100 173kbps (typ) i 2 c to i 2 c-master bit-rate setting. 101 339kbps (typ) i 2 c to i 2 c-master bit-rate setting. 110 533kbps (typ) i 2 c to i 2 c-master bit-rate setting. 111 837kbps (typ) i 2 c to i 2 c-master bit-rate setting. d[1:0] i2cslvto 00 64s (typ) i 2 c to i 2 c-slave remote timeout. 10 01 256s (typ) i 2 c to i 2 c-slave remote timeout. 10 1024s (typ) i 2 c to i 2 c-slave remote timeout. 11 no i 2 c to i 2 c-slave remote timeout. downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 95 table 25. register table (continued) register address bits name value function default value 0x1d d[7:3] 00000 reserved 00000 d2 audufbeh 0 audio fifo repeats last audio word when fifo is empty. 0 1 audio fifo outputs all zeroes when fifo is empty. d1 invsck 0 do not invert sck at output. 0 1 invert sck at output. d0 invws 0 do not invert ws at output. 0 1 invert ws at output. 0x1e d[7:0] id 00101xx0 device identiier(max9288 = 0x2a) (max9290 = 0x2c) 00101xx0 (read only) 0x1f d[7:5] 000 reserved 000 (read only) d4 caps 0 not hdcp capable (max9288). (read only) 1 hdcp capable (max9290). d[3:0] revision xxxx device revision. (read only) 0x40 to 0x59 d[7:0] avinfo xxxxxxxx video/audio format/status/information bytes. all zeroes 0x60 d[7:6] vc 00 csi-2 outputs with id as virtual channel 0. 00 01 csi-2 outputs with id as virtual channel 1. 10 csi-2 outputs with id as virtual channel 2. 11 csi-2 outputs with id as virtual channel 3. d5 inputbw 0 raw8/10/12 mode uses single load. yuv422- 8b/10b uses muxed mode. 0 1 raw8/10/12 mode uses double load. yuv422- 8b/10b uses normal mode. d4 oldi 0 rgb888 uses vesa format (msb to lsb bit order = 7, 6, 5, 4, 3, 2, 1, 0). 1 1 rgb888 uses oldi format (msb to lsb bit order = 5, 4, 3, 2, 1, 0, 7, 6). d[3:0] datatype 0000 csi-2 output uses rgb888 (power-on default) . 0000 0001 csi-2 output uses rgb565. 0010 csi-2 output uses rgb666. 0011 csi-2 output uses yuv 422 8-bit. 0100 csi-2 output uses yuv 422 10-bit. 0101 csi-2 output uses raw8. 0110 csi-2 output uses raw10. 0111 csi-2 output uses raw12. 1000 csi-2 output uses raw14. 1001 csi-2 output uses user deined generic 24-bit (0x30). 1010 csi-2 output uses user deined yuv422 12-bit (0x30). 1011 csi-2 output uses user deined generic 8-bit (0x31). 11xx do not use. downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 96 table 25. register table (continued) register address bits name value function default value 0x61 d[7:0] pixelcntlow xxxxxxxx low byte of pixel count. set this register according to the pixel count per line. 00000000 0x62 d[7:0] pixelcnthigh xxxxxxxx high byte of pixel count. set this register according to the pixel count per line. 00000000 0x63 d[7:6] tclkprepare 00 drive clock lane lp00 for 64ns before starting hs transmission 00 01 drive clock lane lp00 for 72ns before starting hs transmission. 10 drive clock lane lp00 for 80ns before starting hs transmission. 11 drive clock lane lp00 for 88ns before starting hs transmission. d[5:4] tclkzero 00 drive hs0 state for 360ns + 16-24ui before starting the clock. 00 01 drive hs0 state for 720ns + 16-24ui before starting the clock. 10 drive hs0 state for 1.08s + 16-24ui before starting the clock. 11 drive hs0 state for 1.44s + 16-24ui before starting the clock. d[3:0] 0000 reserved 0000 downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 97 table 25. register table (continued) register address bits name value function default value 0x64 d[7:6] thsprepare 00 drive data lane lp00 for 64ns +4ui before starting hs transmission. 00 01 drive data lane lp00 for 72ns + 4ui before starting hs transmission. 1x drive data lane lp00 for 80ns + 4ui before starting hs transmission. d[5:4] thszero 00 drive hs0 state for 160ns + 24 - 32ui before transmitting the sync sequence. 00 01 drive hs0 state for 176ns + 24 - 32ui before transmitting the sync sequence. 10 drive hs0 state for 200ns + 24 - 32ui before transmitting the sync sequence. 11 drive hs0 state for 240ns + 24 - 32ui before transmitting the sync sequence. d[3:2] thstrail 00 drive hstrail state for 64ns + 8ui after the last payload data bit of a hs transmission burst. 00 01 drive hstrail state for 80ns + 8ui after the last payload data bit of a hs transmission burst. 10 drive hstrail state for 96ns + 8ui after the last payload data bit of a hs transmission burst. 11 drive hstrail state for 120ns + 8ui after the last payload data bit of a hs transmission burst. d[1:0] tlpx 00 64ns lptx period length. 00 01 128ns lptx period length. 10 192ns lptx period length. 11 256ns lptx period length 0x65 d7 0 reserved 0 d6 desel 0 normal de operation. 0 1 hs input is the de source. d[5:4] datalanen 00 data lane d0 enabled. 01 01 data lanes d0, d1 enabled. 10 data lanes d0Cd2 enabled. 11 data lanes d0Cd3 enabled. d[3:0] 0111 reserved 0111 downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 98 table 25. register table (continued) register address bits name value function default value 0x66 d[7:6] d3lanemap 00 data-byte 3 maps to lane 0 (data mapping should be exclusive). 11 01 data-byte 3 maps to lane 1. 10 data-byte 3 maps to lane 2. 11 data-byte 3 maps to lane 3. d[5:4] d2lanemap 00 data byte 2 maps to lane 0 (data mapping should be exclusive). 10 01 data byte 2 maps to lane 1. 10 data byte 2 maps to lane 2. 11 data byte 2 maps to lane 3. d[3:2] d1lanemap 00 data byte 1 maps to lane 0 (data mapping should be exclusive). 01 01 data byte 1 maps to lane 1. 10 data byte 1 maps to lane 2 11 data byte 1 maps to lane 3. d[1:0] d0lanemap 00 data byte 0 maps to lane 0 (data mapping should be exclusive). 00 01 data byte 0 maps to lane 1. 10 data byte 0 maps to lane 2. 11 data byte 0 maps to lane 3. 0x67 d[7:0] 00000000 reserved 00000000 0x68 d[7:0] 11001000 reserved 11001000 0x69 d[7:0] 00000000 reserved 00000000 0x6a d[7:0] 00000000 reserved 00000000 0x72 d[7:0] xxxxxxxx reserved xxxxxxxx (read only) 0x73 d[7:0] xxxxxxxx reserved xxxxxxxx (read only) 0x74 d[7:0] xxxxxxxx reserved xxxxxxxx (read only) 0x75 d[7:0] xxxxxxxx reserved xxxxxxxx (read only) 0x76 d[7:4] 0000 reserved 0000 (read only) d[3:2] lfneg 00 negative cable wire shorted to supply voltage. 00 (read only) 01 negative cable wire shorted to ground. 10 normal operation. 11 negative cable wire disconnected. d[1:0] lfpos 00 positive cable wire shorted to supply voltage. 00 (read only) 01 positive cable wire shorted to ground. 10 normal operation. 11 positive cable wire disconnected. downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 99 table 25. register table (continued) register address bits name value function default value 0x77 d[7:0] xxxxxxxx (read only) 0x78 d[7:0] audouper xxxxxxxx audio fifo last overlow/underlow period (audiomode = 1 only). (read only) 0x79 d7 audou 0 audio fifo is in underlow (audiomode = 1 only). (read only) d[6:5] 00 reserved 00 (read only) d4 applerr 0 no pixels-per-line error. 0 (read only) 1 pixels-per-line error detected. d3 prbsok 0 max9271/max9273-compatible prbs test not completed (or completed without success). 0 (read only) 1 max9271/max9273-compatible prbs test completed with success. d2 dlocked 0 de tracking not locked. 0 (read only) 1 de tracking locked. d1 vlocked 0 vs tracking not locked. 0 (read only) 1 vs tracking locked. d0 hlocked 0 hs tracking not locked. 0 (read only) 1 hs tracking locked. 0x7b d[7:0] lutaddr xxxxxxxx lut start address for write and read. 00000000 0x7c d[7:4] 0000 reserved 0000 d3 lutprog 0 disable lut write and read. 0 1 enable lut write and read. d2 bluluten 0 disable blue lut. 0 1 enable blue lut. d1 grnluten 0 disable green lut. 0 1 enable green lut. d0 redluten 0 disable red lut. 0 1 enable red lut. 0x7d d[7:0] redlut xxxxxxxx red lut value (see table 13). 00000000 0x7e d[7:0] greenlut xxxxxxxx green lut value (see table 13). 00000000 0x7f d[7:0] bluelut xxxxxxxx blue lut value (see table 13). 00000000 downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 100 table 26. hdcp register table (max9290 only) register address size (bytes) name read/ write function default value (hex) 0x80 to 0x84 5 bksv read only hdcp receiver ksv. (read only) 0x85 to 0x86 2 ri read only link veriication response. (read only) 0x87 1 pj read only enhanced link veriication response. (read only) 0x88 to 0x8f 8 an read/write session random number. 0x0000000000000000 0x90 to 0x94 5 aksv read/write hdcp transmitter ksv. 0x0000000000 0x95 1 bctrl read/write d7 = pd_hdcp 1 = power down hdcp circuits 0 = hdcp circuits normal 0x00 d[6:4] = reservedd3 = gpio1_function 1 = gpio1 mirrors auth_started 0 = normal gpio1 operation d2 = gpio0_function 1 = gpio0 mirrors encryption_ enable 0 = normal gpio0 operation d1 = auth_started 1 = authentication started (triggered by write to aksv) 0 = authentication not started d0 = encryption_enable 1 = enable encryption 0 = disable encryption 0x96 1 bstatus read/write d[7:2] = reserved 0x00 d1 = new_dev_conn1 = set to 1 if a new connected device is detected. 0 = set to 0 if no new device is connected. d0 = ksv_list_ready 1 = set to 1 if ksv list and binfo is ready 0 = set to 0 if ksv list or binfo is not ready. downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 101 table 26. hdcp register table (max9290 only) register address size (bytes) name read/ write function default value (hex) 0x97 1 bcaps read/write d[7:1] = reserved 0x00 d0 = repeater 1 = set to one if device is a repeater. 0 = set to zero if device is not a repeater. 0x98 to 0x9f 8 read only reserved 0x0000000000000000 (read only) 0xa0 to 0xa3 4 v.h0 read/write h0 part of sha-1 hash value 0x00000000 0xa4 to 0xa7 4 v.h1 read/write h1 part of sha-1 hash value 0x00000000 0xa8 to 0xab 4 v.h2 read/write h2 part of sha-1 hash value 0x00000000 0xac to 0xaf 4 v.h3 read/write h3 part of sha-1 hash value 0x00000000 0xb0 to 0xb3 4 v.h4 read/write h4 part of sha-1 hash value 0x00000000 0xb4 to 0xb5 2 binfo read/write d[15:12] = reserved 0x0000 d11 = max_cascade_exceeded 1 = set to 1 if more than seven cascaded devices attached. 0 = set to 0 if seven or fewer cascaded devices attached. d[10:8] = depth depth of cascaded devices d7 = max_devs_exceeded 1 = set to one if more than 14 devices attached 0 = set to zero if 14 or fewer devices attached d[6:0] = device_count number of devices attached 0xb6 1 gpmem read/write general-purpose memory byte. 0x00 0xb7 to 0xb9 3 read only reserved 0x000000 0xba to 0xff 70 ksv_list read/write list of ksvs downstream repeaters and receivers (maximum of 14 devices). all zero downloaded from: http:///
max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output www.maximintegrated.com maxim integrated 102 /v denotes an automotive qualified product. +denotes a lead(pb)-free/rohs-compliant package. **ep = exposed pad. ?hdcp parts require registration with digital content protection, llc. part temp range pin-package hdcp max9288 ggm/vy+ -40c to +105c 48 qfnd-ep** no max9288gtm+ -40c to +105c 48 tqfn-ep** no max9288gtm/v+ -40c to +105c 48 tqfn-ep** no max9290 gtm+ -40c to +105c 48 tqfn-ep** yes ? max9290gtm/v+ -40c to +105c 48 tqfn-ep** yes ? package type package code outline no. land pattern no. 48 tqfn-ep t4877+4 21-0144 90-0130 48 qfnd-ep g4877y+3 21-0585 90-0457 no te : not a ll pu ll up/pu ll down r es istors are shown. see pin d es cr iption for details. ca me ra app li ca tio n se nsor din0Cdin26 pclkin rx/sda tx /scl gpo out+ out- 49.9? 1.8v conf0C conf3 rgb 88 8 f sy nc i 2 c se nsor coproc ess or i 2 c max 927 5 max 927 9 49.9k? 1.8v in+ in- lmn0 dc lk+/- dout0C dout3+/- rx/sda tx /scl gpi i2c se l cx/ tp cd s 45.3k? 4.99k? 49 .9? max 928 8 max 929 0 f sy nc i 2 c app lications proc ess or csi-2 typical application circuit ordering information package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. chip information process: cmos downloaded from: http:///
maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and speciications without n otice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. max9288/max9290 3.12gbps gmsl deserializers for coax or stp input and mipi csi-2 output ? 2015 maxim integrated products, inc. 103 revision number revision date description pages changed 0 3/14 initial release 1 9/14 added simpliied diagram, removed table 1 and renumbered the subsequent tables, clariied functions, removed future product designations, and corrected typos 1, 28, 33, 48, 49, 51C56, 59, 66, 67, 69C72, 74C77, 79C82, 84, 85, 86, 88C102 2 11/15 clariied timing requirements 8, 27, 30, 50 revision history for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com. downloaded from: http:///

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